Memory cell arrangement and method of fabricating it

Details Memory cell arrangement and method of fabricating it Memory cell arrangement and method of fabricating it

2005-09-13

2005-09-13

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000

Reexamination Certificate

active

06943393

ABSTRACT:
Memory cell arrangement having a memory cell array which has at least one layer of magnetoresistive memory components (11) which are each connected to first contact-making lines (10), the first contact-making lines (10) lying within a first dielectric layer (6), and are each connected to second contact-making lines (20; 29; 35), the second contact-making lines (20; 29; 35) lying within a second dielectric layer (17; 27; 32).

REFERENCES:
patent: 5756366 (1998-05-01), Berg et al.
patent: 5940319 (1999-08-01), Durlam et al.
patent: 6153443 (2000-11-01), Durlam et al.
patent: 197 44095 (1999-04-01), None
patent: 1 054449 (2000-11-01), None
patent: WO 00/31809 (2000-06-01), None
patent: WO 00/38191 (2000-06-01), None
patent: WO 00/52701 (2000-09-01), None
Hu, Y.Z. et al., “Chemical-Mechanical Polishing as an Enabling Technology for Giant Magnetoresistance Devices”,Thin Solid Films, 308-309, pp. 555-561; 1997.

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