Memory cell and production method

Details Memory cell and production method Memory cell and production method

2001-08-09

2004-01-06

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S374000, C257S381000, C257S413000, C257S377000, C257S387000, C257S408000, C438S128000, C438S129000, C438S130000, C438S275000, C438S278000, C438S280000

Reexamination Certificate

active

06674132

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the field of integrated circuits. The invention relates to a nonvolatile flash memory cell that can be written to and erased electrically and has the form of a semiconductor oxide nitride oxide semiconductor (SONOS) cell. The invention also relates to an associated production method.
One aim in the development of memory modules is to specify a memory cell configuration that is as small as possible, but which nevertheless allows rapid random access to individual memory locations. If possible, it should be possible to produce such a memory cell configuration using conventional production technologies, in particular, for the electronic components provided in the drive periphery.
Very small nonvolatile memory cells are required for very large scale integration densities in multimedia applications. Until now, floating gate flash cells using a NAND, AND, or virtual ground NOR architecture have mainly been used, with the smallest memory cells known from products having an area of 5F
2
. The virtual ground configuration, however, does not allow rapid random read access, which requires a low impedance of its (metallic) bit line as far as the individual memory cell. Standard T-shaped cells with a metallic connection require a considerably larger cell area due to the adjustment separations that are required; floating gate cells such as these whose area is 12F
2
are now normal.
The publication “Analysis of Carrier Traps in Si
3
N
4
in Oxide/Nitride/Oxide for Metal/Oxide/Nitride/Oxide/Silicon Nonvolatile Memory” by H. Aozasa et al., in Jpn. J. Appl. Phys. 38, 1441-1447 (1999) describes and investigates a memory layer structure based on an oxide-nitride-oxide layer sequence.
U.S. Pat. No. 5,397,726 to Bergemont describes a flash EPROM in which the memory layer structure is disposed between the semiconductor body and the gate electrode, the source line is provided as a common source connection for a number of memory cells, and a floating gate electrode is provided as the memory layer.
U.S. Pat. No. 6,080,624 to Kamiya et al. describes a nonvolatile semiconductor memory in which a floating gate electrode, provided as a memory layer, is disposed between a gate dielectric and an ONO layer.
U.S. Pat. No. 5,918,124 to Sung discloses the formation of spacing elements for lightly doped drain (LDD) source/drain regions in a multiple memory EEPROM cell.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory cell and production method that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that provides a nonvolatile memory cell for a very large scale integration density, with short access times, and an associated production method.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a memory cell disposed on a semiconductor body having a top face, the memory cell including a source region formed at the top face, a drain region, a gate line, a gate electrode disposed between the source region and the drain region at the top face, the gate electrode being part of the gate line, the gate line structured in strips and being a word line, a source line being a common source connection for a plurality of memory cells, the source line electrically contacting the source region between the gate electrode and another gate electrode of another of the plurality of memory cells, a drain line being a metallic interconnect electrically conductively connected to the drain region and disposed as a bit line running transversely with respect to the gate line and electrically isolated from the gate line, supply leads respectively connected to the source line, the drain line, and the gate line, and a memory layer structure having a first boundary layer, a second boundary layer, and a memory layer disposed in between the first boundary layer and the second boundary layer. The memory layer, the first boundary layer, and the second boundary layer are each made from a material having a respective energy band gap. The material of the memory layer has a relatively narrow energy band gap. The material of the first boundary layer and the second boundary layer has a relatively wide energy band gap. The memory layer structure is disposed between the semiconductor body and the gate electrode.
In other words, the memory cell according to the invention has an ONO layer structure or an equivalent memory layer structure between a gate electrode and the channel region formed in the semiconductor body. The gate electrode is a component of a word line in strip form. There are source and drain regions between the gate electrodes of adjacent memory cells. The source regions are provided with polysilicon layers that are in strip form and are connected between the gate electrodes to provide common source lines. The drain regions are connected through polysilicon fillings to metallic interconnects that are applied to the top face as bit lines. In the transverse direction with respect to the sequence of the source region, gate electrode, and drain region, the individual cells in a memory cell configuration are isolated from one another by narrow isolation trenches (STI, shallow trench isolation). A preferred production method is particularly suitable for integration in a production process by which the electronic drive components in the periphery of the memory are also produced together with the memory cell configuration.
In accordance with another feature of the invention, there are provided isolation trenches in the semiconductor body separating the memory cell in the semiconductor body from further memory cells disposed on both sides of the memory cell in a direction of the gate line.
In accordance with a further feature of the invention, the source region and the drain region each have two sides, a gate electrode is disposed on each of the two sides of the source region and the drain region, the source line is a conductively doped polysilicon layer shaped as a strip and fills a region between the gate electrodes above the source region, a further conductively doped polysilicon layer is shaped as a strip and fills a region between the gate electrodes above the drain region and contacts the metallic drain line, and electrically isolating parting layers are respectively disposed between the gate electrodes and the polysilicon layer and the further polysilicon layer.
In accordance with an added feature of the invention, only one gate electrode is disposed in the memory cell between the polysilicon layer above the source region and the further polysilicon layer above the drain region.
In accordance with an additional feature of the invention, the gate electrode and a further gate electrode, provided as a select-gate electrode, of another memory cell of the plurality of memory cells are disposed in series through a further source region and further drain region of the other memory cell, and the gate electrode and the further gate electrode are disposed between the polysilicon layer above the source region and the further polysilicon layer above the drain region.
In accordance with yet another feature of the invention, the source region and the drain region each have a given dopant concentration, and a lightly doped drain region has a dopant concentration less than the dopant concentration in the source region and in the drain region, the lightly doped drain region is connected to the source region and to the drain region in a direction toward a respectively adjacent gate electrode in another of the plurality of memory cells.
In accordance with yet a further feature of the invention, the memory layer is silicon nitride, and the first boundary layer and second boundary layer are silicon oxide. Alternatively, the memory layer is tantalum oxide or hafnium silicate, and the first boundary layer and second boundary layer are silicon oxide. The memory layer can include hafnium oxide, hafnium silicate, zirconium oxide, or zirconium s

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