Memory cache with low power consumption and method of operation

Details Memory cache with low power consumption and method of operation Memory cache with low power consumption and method of operation

1995-09-05

1996-08-27

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Multiplexing

36518907, 36523002, 36523003, G11C 800

Patent

active

055507743

ABSTRACT:
A memory cache (46) has a plurality of tag arrays (20, 22, 24, 26), a plurality of comparators (38, 40, 42, 44), a plurality a data arrays (12, 14, 16, 18), and a plurality of sense amplifiers (48, 50, 52, 54). The memory cache executes a parallel tag and data array access but does not enable any sense amplifier until a comparator indicates a cache hit. Consequently, the memory cache is suitable for use where power consumption and speed are equally important design constraints.

REFERENCES:
patent: 4804871 (1989-02-01), Walters, Jr.
patent: 5111386 (1992-05-01), Fujishima et al.
patent: 5253203 (1993-10-01), Partovi et al.
patent: 5497347 (1996-03-01), Feng

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