Memory bus shared system

Details Memory bus shared system Memory bus shared system

2011-07-19

2011-07-19

Du, Thuan (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C710S305000, C711S168000

Reexamination Certificate

active

07984319

ABSTRACT:
The invention reduces the pin terminal number of a controller that in parallel or simultaneously accesses a synchronous memory and an asynchronous memory. When a column address is latched to an SDRAM, immediately after that, access to FLASH is started, and a shared bus controller outputs the write/read address with respect to FLASH on the address bus. Then, after the end of data transfer on the data bus, either the shared bus controller outputs the write data, or FLASH can output the read data on the data bus by means of a strobe signal. Then, the input of address is established by FLASH, and, as the shared bus controller asserts a strobe signal, either FLASH fetches the write data on the data bus, or the shared bus controller fetches the read data on the data bus.

REFERENCES:
patent: 6625716 (2003-09-01), Fackenthal
patent: 7185133 (2007-02-01), Teranuma et al.
patent: 7426607 (2008-09-01), Oh
Tim Hellman, “SDRAM interface slashes pin count,” design ideas, EDN/Mar. 29, 2001, pp. 132, 134.

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