Memory bus precharging circuit

Details Memory bus precharging circuit Memory bus precharging circuit

1990-12-18

1993-09-07

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Precharge

36518909, 365204, 36523006, 307446, 307480, G11C 700

Patent

active

052435717

ABSTRACT:
A precharging circuit of a memory bus that includes a bipolar transistor driven by a clock signal wherein the base of the bipolar transistor is connected to both supply potentials through two respective complementary field effect transistors having their gates connected to the output of a threshold amplifier connected to the bus. The precharging circuit allows adjustment of the precharging voltage of a memory bus to a value predetermined during the precharging phase of the clock signal.

REFERENCES:
patent: 4813020 (1989-03-01), Iwamura et al.
patent: 4866673 (1989-09-01), Higuchi et al.
patent: 4873673 (1989-10-01), Hori et al.
patent: 5058067 (1991-10-01), Kertis
patent: 5070261 (1991-12-01), Ten Eyck
patent: 5103113 (1992-04-01), Inui et al.

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