Memory bus arbitration using memory bank readiness

Details Memory bus arbitration using memory bank readiness Memory bus arbitration using memory bank readiness

2006-09-12

2006-09-12

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S151000, C711S158000, C710S039000, C710S240000, C710S244000

Reexamination Certificate

active

07107386

ABSTRACT:
A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.

REFERENCES:
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patent: 6249847 (2001-06-01), Chin et al.
patent: 6269433 (2001-07-01), Jones et al.
patent: 6295586 (2001-09-01), Novak et al.
patent: 6385692 (2002-05-01), Banks et al.
patent: 6499090 (2002-12-01), Hill et al.
patent: 2002/0184455 (2002-12-01), Cho

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