Memory built-in self test engine apparatus and method with...

Details Memory built-in self test engine apparatus and method with... Memory built-in self test engine apparatus and method with...

2007-02-20

2007-02-20

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S733000

Reexamination Certificate

active

11055195

ABSTRACT:
A memory built-in self test (MBIST) apparatus and method for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic. The MBIST apparatus includes a finite state machine including a command generator and logic for incrementing data and addresses under test and a command scheduler in communication with the finite state machine. The command scheduler includes resource allocation logic for spacing commands to memory dynamically utilizing DRAM timing parameters. The MBIST apparatus also includes a test memory storing subtests of an MBIST test. Each of the subtests provides a full pass through a configured address range. The MBIST apparatus further includes a subtest pointer in communication with the test memory and the finite state machine. The finite state machine implements subtest sequencing of each of the subtests via the subtest pointer.

REFERENCES:
patent: 6553527 (2003-04-01), Shephard, III
patent: 6834361 (2004-12-01), Abbott
patent: 7036064 (2006-04-01), Kebichi et al.
patent: 7039545 (2006-05-01), Bundy et al.
patent: 7114024 (2006-09-01), Herbst

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