Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
2004-02-11
2009-12-01
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C365S201000
Reexamination Certificate
active
07627792
ABSTRACT:
A method for repairing a memory comprising a Memory Built-In Self Repair (MBISR) structure comprises the steps of detection of defective storage cells, and redundancy allocation. The redundancy allocation step is carried out in such a way that it combines a row and/or column oriented redundancy repair approach with a word oriented redundancy repair approach. A Memory Built-In Self Repair (MBISR) device comprises at least one memory (2) with row and/or column redundancy, at least one row and/or column Memory Built-In Self Repair (MBISR) circuit (3), and a word redundancy block (4). Furthermore, a distributed MBISR structure as well as dedicated Column/Row MBISR circuits (3) are provided.
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Di Ronza Mario
Martelloni Yannick
Britt Cynthia
Infineon - Technologies AG
Patterson & Sheridan L.L.P.
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