Memory block compaction method, circuit, and system in...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C711S154000, C711S156000, C711S206000, C714S005110

Reexamination Certificate

active

07991942

ABSTRACT:
A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space.

REFERENCES:
patent: 4800520 (1989-01-01), Iijima
patent: 5107481 (1992-04-01), Miki et al.
patent: 5471604 (1995-11-01), Hasbun et al.
patent: 5479633 (1995-12-01), Wells
patent: 5566314 (1996-10-01), DeMarco et al.
patent: 5832493 (1998-11-01), Marshall et al.
patent: 5867641 (1999-02-01), Jenett
patent: 6104638 (2000-08-01), Larner et al.
patent: 6170066 (2001-01-01), See
patent: 6449625 (2002-09-01), Wang
patent: 6513095 (2003-01-01), Tomori
patent: 6834331 (2004-12-01), Liu
patent: 6895490 (2005-05-01), Moore et al.
patent: 6973531 (2005-12-01), Chang et al.
patent: 7035993 (2006-04-01), Tai et al.
patent: 7353325 (2008-04-01), Lofgren et al.
patent: 7457909 (2008-11-01), Di Sena et al.
patent: 2002/0199054 (2002-12-01), Akahane et al.
patent: 2003/0093606 (2003-05-01), Mambakkam et al.
patent: 2003/0158862 (2003-08-01), Eshel et al.
patent: 2003/0165076 (2003-09-01), Gorobets et al.
patent: 2004/0001370 (2004-01-01), Nakayama
patent: 2004/0039872 (2004-02-01), Takamizawa et al.
patent: 2004/0078666 (2004-04-01), Aasheim et al.
patent: 2004/0255090 (2004-12-01), Guterman et al.
patent: 2004/0268064 (2004-12-01), Rudelic
patent: 2005/0289558 (2005-12-01), Illowsky et al.
patent: 2006/0031710 (2006-02-01), Jo
patent: 2006/0106972 (2006-05-01), Gorobets et al.
patent: 2006/0155917 (2006-07-01), Di Sena et al.
patent: 2006/0161723 (2006-07-01), Sena et al.
patent: 2006/0184719 (2006-08-01), Sinclair
patent: 2006/0271725 (2006-11-01), Wong
patent: 2007/0016721 (2007-01-01), Gay
patent: 2007/0033329 (2007-02-01), Sinclair et al.
patent: 2007/0033374 (2007-02-01), Sinclair et al.
patent: 2007/0083697 (2007-04-01), Birrell et al.
patent: 2007/0113001 (2007-05-01), Yamada
patent: 2007/0143531 (2007-06-01), Atri
patent: 2007/0174549 (2007-07-01), Gyl et al.
patent: 2007/0300037 (2007-12-01), Rogers et al.
patent: 2008/0235306 (2008-09-01), Kim et al.
patent: 2008/0282025 (2008-11-01), Biswas et al.
U.S. Appl. No. 12/075,991, filed May 9, 2007, titled, “Wear Leveling in Storage Devices Based on Flash Memories and Related Circuit, System, and Method”.
U.S. Appl. No. 11/801,687, filed May 9, 2007, titled, “Restoring Storage Devices Based on Flash Memories and Related Circuit, System, and Method”.
U.S. Appl. No. 11/801,742, filed May 9, 2007, titled, “Management of Erase Operations in Storage Devices Based on Flash Memories”.
Gay (2003) “Design of Matchbox, the Simple Filing System for Motes”; www.tinyos.net/tinyos-1.x/doc/matchbox-design.pdf.
Hill (2003) “System Architecture for Wireless Sensor Networks”; UNIV. of California, Berkeley.
Kim et al. (1999) “A New Flash Memory Management for Flash Storage System”; IEEE; COMPSAC '99.
Mathur et al. (2006) “Capsule: An Energy-Optimized Object Storage System for Memory-Constrained Sensor Devices”; ACM; Sensys '06.
Brown et al. (2000) “Fundamentals of Digital Logic With VHDL Design”; McGraw-Hill Higher Education; pp. 2-6.
Gal et al. (Jun. 2005) “Algorithms and Data Structures for Flash Memories”; ACM Computing Surveys; 37(2):138-163.
Manning et al. (Feb. 2002) “YAFFS (Yet Another Flash File System)”; http://YAFFS.net; 15 Pages.
Kang et al. (Oct. 22-25, 2006) “A Superblock-Based Flash Translation Layer for Nand Flash Memory”; ACM; EMSOFT '06; Seoul, Korea; pp. 161-170.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Memory block compaction method, circuit, and system in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory block compaction method, circuit, and system in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory block compaction method, circuit, and system in... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2724461

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.