Static information storage and retrieval – Read/write circuit – Multiplexing
Patent
1990-02-26
1991-10-15
Gossage, Glenn
Static information storage and retrieval
Read/write circuit
Multiplexing
365194, 36518912, 340800, 340802, G11C 700, G11C 1900
Patent
active
050580655
ABSTRACT:
A digital line delay architecture is provided that requires a minimum of chip space, has low power requirements, is variable or programmable in length, and is flexible to permit changes in aspect ratio. The digital line delay architecture is self-multiplexing and therefore requires no external addressing for the multiplexing function, and is particularly suited for use as a video line delay in a single chip digital image processing device. In particular, a pointer unit is employed to sequentially address a plurality of word storage locations provided in a storage unit. The pointer unit includes a number of shift-registers that sequentially shift a logic "1" along the length of the pointer unit to accomplish the addressing.
REFERENCES:
patent: 4237547 (1980-12-01), Smith
patent: 4321695 (1982-03-01), Redwine et al.
patent: 4648077 (1987-03-01), Pinkham et al.
patent: 4691302 (1987-09-01), Mattausch
patent: 4740924 (1988-04-01), Tielert
patent: 4748595 (1988-05-01), Mattausch
patent: 4782247 (1988-11-01), Yoshida
patent: 4794559 (1988-12-01), Greenberger
patent: 4803663 (1989-02-01), Miyamoto et al.
patent: 4876670 (1989-10-01), Nakabayashi et al.
Mattausch et al., A Memory-Based High-Speed Digital Delay Line With a Large Adjustable Length, IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988, pp. 105-110.
Ruetz et al., Architectures and Design Technique for Real-Time Image-Processing IC's, IEEE Journal of Solid-State Circuits, vol. sc-22, No. 2, Apr. 1987, pp. 233-250.
Zehner et al., A CMOS VLSI Chip for Filtering of TV Pictures in Two Dimensions, IEEE Journal of Solid-State Circuits, vol. sc-21, No. 5, Oct. 1986, pp. 797-802.
Eastman Kodak Company
Gossage Glenn
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