Memory array with salicide isolation

Details Memory array with salicide isolation Memory array with salicide isolation

2001-05-31

2003-07-29

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S241000, C438S244000, C438S360000, C438S255000, C438S258000

Reexamination Certificate

active

06599793

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to memory array, and more particularly to memory array with salicide isolation.
2. Description of the Prior Art
In many applications, an electronic device includes a logic circuit device and a memory device, which are separately fabricated in different individual semiconductor substrates. As the technologies of semiconductor fabrication are further developed, a new trend has developed in which the logic circuit device and the memory device are fabricated in a single substrate so as to enhance the operation speed.
However, the fabrication processes for the logic device and the memory device are different. The logic device mainly used for a logic operation needs a fast data transmission speed, and therefore needs a self-aligned (Salicide), such as titanium silicide, formed over the interchangeable source/drain regions to reduce sheet resistance. The memory device mainly used for storing information data needs to avoid leakage current, which leakage current may cause a change of data, and so the interchangeable source/drain regions must not have silicide. Thus, layout of logic circuit device integrated with memory device in a single substrate needs to be modified when the conventional CMOS salicide process is applied.
Accordingly, it is important to prevent buried diffusion regions in the memory device from short effect and reduce loading of the memory cell for improving the performance thereof when the conventional CMOS self-aligned salicide process is applied on the fabrication of the memory array.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a memory array fabricated by complementary metal-oxide-semiconductor salicide process. The coordination of shallow trench isolation and LOCOS structure can prevent salicide from short.
It is another object of the present invention to provide a virtual ground flash memory fabricated by complementary metal-oxide-semiconductor salicide process. A conductive contact is periodically located on N+ diffusion region instead of buried diffusion oxide.
In the present invention, a memory array is fabricated by complementary metal-oxide-semiconductor salicide process. The memory array comprises a semiconductor substrate. Multitudes of first isolation devices are aligned in the semiconductor substrate and second isolation devices aligned on the semiconductor substrate. The alignment of the second isolation devices is parallel to one of the first isolation devices. Some polysilicon lines are on the second isolation devices therefor have null memory function. A conductive structure is below a surface of the semiconductor substrate. The conductive structure is located between the first isolation devices. A conductive contact is on the conductive structure. The correspondence of the first isolation devices and the polysilicon lines can prevent the conductive structures from short effect.


REFERENCES:
patent: 6395596 (2002-05-01), Chien et al.
patent: 6413861 (2002-07-01), Huang et al.
patent: 6436765 (2002-08-01), Liou et al.

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