Memory array with precharge control circuit

Details Memory array with precharge control circuit Memory array with precharge control circuit

2007-07-03

2007-07-03

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S063000, C365S133000, C365S185250

Reexamination Certificate

active

10954250

ABSTRACT:
In one embodiment, a memory apparatus is provided with at least one local bit-line; a precharge control circuit, coupled to the at least one local bit-line, and adapted to be operable to initiate a precharge pulse after the at least one local bit-line is discharged and to terminate the precharge pulse after the at least one local bit-line has been precharged; a precharge pull-up device, coupled to the precharge control circuit, a first voltage source, and the at least one local bit-line, and adapted to be operable to connect the first voltage source to the at least one local bit-line during the precharge pulse to precharge the at least one local bit-line; and a selected one of a plurality of evaluation pull-down devices, coupled to a clock source, a second voltage source, and the at least one bit-line, and adapted to be operable to couple the at least one local bit-line to the second voltage source during the clock signal pulse to discharge the at least one local bit-line.

REFERENCES:
patent: 5623450 (1997-04-01), Phillips et al.
patent: 5675529 (1997-10-01), Poole
patent: 5701269 (1997-12-01), Fujii
patent: 6396732 (2002-05-01), Osada et al.
patent: 6434071 (2002-08-01), Labrecque
patent: 6564331 (2003-05-01), Joshi
patent: 6629194 (2003-09-01), Kumar et al.

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