Memory array with fast bit line precharge

Details Memory array with fast bit line precharge Memory array with fast bit line precharge

2006-07-25

2006-07-25

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S189060, C365S185200, C365S185210, C365S185250

Reexamination Certificate

active

07082069

ABSTRACT:
An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Precharge transistors are coupled to respective bit lines in the array, and adapted to precharge voltage on the respective bit lines to near a target level. A detector has an input coupled to the reference bit line and an output coupled to the precharge transistors on the plurality of bit lines. The detector generates a precharge signal which turns off the precharge transistors when the reference bit line has a voltage near the target level, and turns on the precharge transistors when the reference bit line has a voltage below the target level.

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