Memory array with bias voltage generator

Details Memory array with bias voltage generator Memory array with bias voltage generator

1978-03-27

1979-05-29

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365190, G11C 700

Patent

active

041569407

ABSTRACT:
A bias generator produces a voltage (V.sub.R) which is applied to the control electrode of a gating transistor via whose conduction path the contents of a memory cell are read-out. V.sub.R is such that, during read-out, the maximum amplitude of the gate-to-source potential (V.sub.GS) applied to the gating transistor, in a direction to turn it on, is approximately equal to a fraction of the memory cell supply voltage plus an offset voltage comparable to the threshold voltage (V.sub.T) of the gating transistor. The bias generator includes a voltage divider connected across the same supply voltage source as the memory cell. A portion of the supply voltage (K V.sub.DD) generated at a node of the divider is applied to an offset voltage generating circuit which includes as least one device of the same type as the gating transistor and which produces V.sub.R at its output. V.sub.R is approximately equal to K V.sub.DD offset by a voltage comparable to the V.sub.T of the gating transistor. Applying V.sub.R to the gating transistor enables the contents of the memory cell to be read out non-destructively since the ON impedance of the gating transistor is controlled over a wide range of supply voltage variation and for a wide range of device characteristics.

REFERENCES:
patent: 4063225 (1977-12-01), Stewart
Hollingsworth, "Memory Cell", RCA Technical Notes, No. 1125, 8/28/75.

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