Memory array reconfiguration for testing

Details Memory array reconfiguration for testing Memory array reconfiguration for testing

1993-07-27

1994-12-27

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Multiplexing

365201, 36523002, G11C 700

Patent

active

053771443

ABSTRACT:
A memory part (10), with memory (14) subarrays arranged in different ways, provides one data input and output path for normal operation and another data input and output path for test mode operation. The part furnishes one data output multiplexer (40) connected between the memory (14) subarrays and the data output buffers (24) for normal operation. The part furnishes another data output multiplexer (52) connected between the memory (14) subarrays and the data output buffers for test mode operation. Test mode circuits (30) on the memory part select operation of the one and the other multiplexer. Data input gating circuits connect between the data in buffers (22) and the memory (14) subarrays and connect all or one of the data input leads D0-8 to the memory subarrays in response to operation of the test mode circuits.

REFERENCES:
patent: 4873669 (1989-10-01), Furutani
patent: 5079747 (1992-01-01), Nakada
patent: 5089993 (1992-02-01), Neal
patent: 5185720 (1993-02-01), Vaillancourt
patent: 5208778 (1993-05-01), Kumanoya
patent: 5220518 (1993-06-01), Haq
patent: 5228132 (1993-07-01), Neal

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