Memory array organization for static arrays

Details Memory array organization for static arrays Memory array organization for static arrays

2001-02-15

2002-12-24

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S189050

Reexamination Certificate

active

06498754

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to electronic systems. More particularly, the invention relates to a memory array organization for use in an electronic system.
BACKGROUND OF THE INVENTION
Typical memory array organizations are arranged as rows of latches because data is logically arranged in rows. For example, an instruction memory storing 8 eight-bit instruction words, would consist of eight rows of eight latches and associated decode and selection circuitry.
FIG. 1
illustrates an 8×8 memory organized as rows. Such a memory array organization is common in the prior art. However, when designing an application specific integrated circuit (ASIC), memory arrays, along with other circuit elements are synthesized, placed and routed using electronic design automation (EDA) tools. Because of the interconnection of latches and associated clocking signals, these memory arrays are not easily placed and routed.
Write addresses are decoded by address decode circuitry
100
, which generates a write enable signal to cause the latches of a row of memory to latch the incoming data, labeled Write Data in FIG.
1
. Data is read from the memory array by selecting the desired row from read multiplexer
120
.
FIG. 2
illustrates an embodiment of a row of memory in the memory array of FIG.
1
.
FIG. 2
illustrates that each latch in each row of the memory array receives a gated clock signal to enable the latches. Given that the latches in any given row share a gated clock, it is necessary to place the latches in each row in very close proximity to each other, in order to control clock skew and limit the amount of place and route resources that must be dedicated to clock distribution within the array. Therefore, placement of the array of
FIGS. 1 and 2
are placed to optimize clock routing lines, which increases the routing required to couple the latches to the read multiplexer.
SUMMARY OF THE INVENTION
A memory array having a plurality of latches is organized in columns and rows, the rows store contiguous bits of data. The memory array includes a first subset of latches and a second subset of latches. The first subset of latches represents a first column of data coupled to a first multiplexer to select signals from one of the first subset of latches. The first subset of latches is coupled to receive a first clock signal. The second subset of latches represents a second column of data coupled to a second multiplexer to select signals from the second subset of latches. The second subset of latches is coupled to receive a second clock signal.


REFERENCES:
patent: 5083119 (1992-01-01), Trevett et al.
patent: 5568432 (1996-10-01), Wada
patent: 5848005 (1998-12-01), Cliff et al.
patent: 6064599 (2000-05-01), Cliff et al.
patent: 6292116 (2001-09-01), Wang et al.

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