Memory array having shallow bit line with silicide contact...

Details Memory array having shallow bit line with silicide contact... Memory array having shallow bit line with silicide contact...

2003-03-05

2004-06-01

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S384000, C257S456000, C257S486000, C257S576000, C257S768000, C257S757000, C438S300000, C438S048000, C438S092000, C438S570000, C438S648000, C438S650000

Reexamination Certificate

active

06744105

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the field of non-volatile memory devices and, more particularly, to a charge trapping dielectric core memory array which can have shallow bit lines and silicide contact portions. Certain aspects of the present invention relate to a method of fabricating a core memory array.
BACKGROUND
A pervasive trend in modern integrated circuit manufacture is to increase the amount of data stored per unit area on an integrated circuit memory unit, such as a flash memory unit. Memory units often include a relatively large number of core memory devices (sometimes referred to as core memory cells). For instance, a conventional dual cell memory device, such as a charge trapping dielectric flash memory device, can store data in a “double-bit” arrangement. That is, one bit can be stored using a first charge storing region on a first “side” of the memory device and a second bit can be stored using a second charge storing region on a second “side” of the memory device.
In a conventional charge trapping dielectric flash memory device, the charge storing regions are part of a nonconductive charge trapping layer that is disposed between a bottom (or tunnel) dielectric layer and a top dielectric layer. This dielectric stack can be formed over a P conductivity type silicon substrate having a series of bit lines disposed therein. The bit lines can be formed by implanting impurities into the substrate to form N+ conductivity regions. In conventional charge trapping dielectric core memory arrays, the bit lines are implanted through each of the top dielectric layer, charge trapping layer and bottom dielectric layer with relatively high energy ions.
A series of conductive word lines made from polycrystalline silicon (also referred to as poly-silicon or poly-Si) is formed over the dielectric stack for serving as a gate electrode for each memory device. The core memory devices can be addressed by applying appropriate voltages to the word line and/or the bit lines. During programming and reading of the core memory devices, the bit lines can function as a source (i.e. source of electrons or holes) and a drain with an active channel region defined therebetween.
Between a predetermined number of word lines, conductive vias can traverse the dielectric stack to establish electrical contact to the bit lines. For bit lines made from N+ conductivity silicon, sets of vias (one via for each bit line) can be placed at intervals of about eight to about sixteen word lines. More specifically, the sets of vias are placed sufficiently close together to minimize adverse effects of bit line resistance (e.g., about 100 ohms/cm
2
for N+ doped silicon) on programming and reading of core memory devices that are relatively remote from the vias. However, the vias consume value room within the core memory array. In effect, the vias displace word lines that, along with respect pairs of bit lines, can be used to operatively form core memory devices.
In view of the foregoing, there is a need in the art for an improved core memory array with a reduced number of vias and method of forming same.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is directed to a core memory array having a plurality of charge trapping dielectric memory devices. The core memory array can include a substrate having a first semiconductor bit line and a second semiconductor bit line formed therein and a body region interposed between the first and the second bit lines; a first dielectric layer disposed over the body region; a dielectric charge trapping layer disposed over the first dielectric layer, a second dielectric layer disposed over the charge trapping layer; at least one word line disposed over the second dielectric layer and defining a channel within the body region, and for each bit line, a bit line contact assembly including a locally metalized portion of the bit line and a conductive via traversing a dielectric region.
According to another aspect of the invention, the invention is directed to a method of fabricating a core memory array. The method can include providing a substrate; forming a first dielectric layer over the substrate; forming a dielectric charge storing layer over the first dielectric layer; forming a second dielectric layer over the charge storing layer; removing portions of the at least the second dielectric layer and the charge trapping layer to form at least two longitudinally disposed bit line implant windows; and implanting impurities into the substrate to form bit lines in the substrate and defined by the implant windows.


REFERENCES:
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patent: 6215702 (2001-04-01), Derhacobian et al.
patent: 6309926 (2001-10-01), Bell et al.
patent: 6320261 (2001-11-01), Burton et al.
patent: 6344994 (2002-02-01), Hamilton et al.
patent: 6456533 (2002-09-01), Hamilton et al.
patent: 6495921 (2002-12-01), Burton et al.
patent: 6645801 (2003-11-01), Ramsbey et al.

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