Memory array apparatus with reduced data accessing time and...

Details Memory array apparatus with reduced data accessing time and... Memory array apparatus with reduced data accessing time and...

2001-08-02

2004-04-06

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

C710S037000, C710S038000, C710S058000

Reexamination Certificate

active

06718406

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a memory array apparatus, especially to a memory array apparatus with shorter data accessing time to reduce waiting of a main frame, and method for the same.
BACKGROUND OF THE INVENTION
The flash memory has the advantages of compact size, low power consumption, shock resistance and non-volatility, and is suitable for portable electronic devices such as personal communication apparatus and palm computer.
FIG. 1
shows a conventional flash memory array apparatus, which mainly comprises an interface controller
13
, a micro-controller
15
, a data register
17
, a data input/output port
18
and a flash memory array
19
. The interface controller
13
of the flash memory array apparatus is connected to a main frame
10
through a bus
11
. When data is to be stored into the flash memory array
19
, the main frame
10
commands the micro-controller
15
to divide the data to be stored into a plurality of data blocks according to a predetermined data unit such as 512 bytes. Each data block is firstly stored in the data register
17
and then stored into the flash memory array
19
through the data input/output port
18
. On the contrary, the data transmission path is reversed when the data is to be read.
However, in above-mentioned flash memory array apparatus, the data transmission speed between the data register
17
and the flash memory array
19
is relatively low. Moreover, the above-mentioned flash memory array apparatus is designed to have single data register
17
and single flash memory array
19
, the main frame
10
requires a waiting time before the data transmission between the data register
17
and the flash memory array
19
is completed. The data accessing speed is not satisfactory.
SUMMARY OF THE INVENTION
It is the object of the present invention to provide a memory array apparatus with shorter data accessing time to reduce waiting of a main frame, and method for the same.
In one aspect of the present invention, the data to be accessed is divided into a plurality of data blocks and a plurality of data registers are used to store temporarily the separate data block. The data accessing time between the memory array and the data register is exploited to the data transmission for the next data block, whereby the waiting time of main frame can be reduced.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing, in which:


REFERENCES:
patent: 5012408 (1991-04-01), Conroy
patent: 5060145 (1991-10-01), Scheuneman et al.
patent: 5263003 (1993-11-01), Cowles et al.
patent: 5987573 (1999-11-01), Hiraka
patent: 6215727 (2001-04-01), Parson et al.

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