Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2002-02-28
2004-04-06
Cho, James H (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S040000, C714S726000
Reexamination Certificate
active
06717433
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fields of field programmable gate array (FPGA) and emulation systems.
2. Background Information
Emulation systems for emulating circuit design are known in the art. Typically, prior art emulation systems are formed using general purpose FPGAs without integrated debugging facilities. A circuit design to be emulated is “realized” on the emulation system by compiling a “formal” description of the circuit design, and mapping the circuit design onto the logic elements (LEs) of the FPGAs.
These general purpose FPGAs, as far as their applications to emulation systems are concerned, have a number of disadvantages. First of all, the states of signals at the nodes mapped inside the FPGAs are not directly observable, thus the term “hidden” nodes. Secondly, in order to be able to observe the states of signals at these “hidden” nodes, reconfiguration, and therefore extremely time consuming recompilation is required to bring these signals outside the FPGAs to a logic analyzer. Thirdly, a number of the FPGA I/Os will have to be consumed for bringing these signals to the logic analyzer. Furthermore, the additional signals to be routed further increase signal routing congestion. Finally, for timing sensitive applications, it is difficult to know whether the signals at these “hidden” nodes were read at precisely the correct time or not, if the signals are to be read in response to the occurrence of certain events, since the signals have to be brought out of the FPGAs before the read triggering events can be detected.
Thus, it is desirable to have an improved FPGA with integrated debugging facilities that is more suitable for usage by the emulation systems. As will be described in more detail below, the present invention provides for such an improved FPGA with integrated debugging facilities that achieves these and other desired results, which will be apparent to those skilled in the art from the description to follow.
SUMMARY OF THE INVENTION
An improved FPGA having integrated debugging facilities is disclosed. The improved FPGA comprises a number of enhanced logic elements (LEs) interconnected to each other, preferably, via a network of crossbars. Each enhanced LE comprises a multiple input-single output truth table and a complementary pair of master-slave latches having a data, a set and a reset input, and control logic. As a result, the enhanced LE may be used for “level sensitive” as well as “edge sensitive” circuit design emulations. Each enhanced LE further comprises a plurality of multiplexors and buffers, allowing each LE to be individually initialized, its state to be froze momentarily, and the frozen state to be read or modified.
Additionally, the improved FPGA further comprises a complementary context bus and read/write facilities for setting the enhanced LEs' initial values, and for reading of their frozen states. The improved FPGA also comprises a scan register for outputting trace data for the enhanced LEs. Lastly, the improved FPGA also comprises a plurality of trigger circuitry for conditionally generating a plurality of trigger inputs.
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Barbier Jean
LePape Olivier
Reblewski Frederic
Banner & Witcoff , Ltd.
Cho James H
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