Memory architecture of display device and memory writing...

Details Memory architecture of display device and memory writing... Memory architecture of display device and memory writing...

2007-09-11

2007-09-11

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230050, C345S098000

Reexamination Certificate

active

11082758

ABSTRACT:
A memory architecture of display device comprises a memory cell array having a plurality of memory cells arranged as a plurality of cell rows and a plurality of cell columns, and a data latch circuit having a plurality of latch units for storing a plurality of bits; wherein the number of the latch units is equal to that of the memory cells in each cell row, such that each bit stored in the data latch circuit can be written to each memory cell of one cell row at one time. The present invention also provides a memory writing method.

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