Memory architecture and systems and methods using the same

Details Memory architecture and systems and methods using the same Memory architecture and systems and methods using the same

1997-12-17

1999-08-17

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365203, 365207, 36523003, G11C 700

Patent

active

059403292

ABSTRACT:
A memory architecture 400 includes an array of memory cells partitioned into a plurality of subarrays 401. Each subarray 401 includes a plurality of memory cells organized in rows and columns, each row associated with a conductive wordline 407 and each column associated with a pair of conductive half-bitlines 403. The first sense amplifier 402 is selectively coupled to selected pair of half-bitlines 403. A second sense amplifier 402 is selectively coupled to the selected pair of half-bitlines 403. A first local I/O line 404 is coupled to first sense amplifier 402 and a second local I/O line 404 is coupled to the second sense amplifier 402. First and second sets of global I/O lines 405 are selectively coupled to the first and second I/O lines 404.

REFERENCES:
patent: 5636174 (1997-06-01), Rao
patent: 5748554 (1998-05-01), Barth et al.
patent: 5835441 (1998-11-01), Seyyedy et al.
patent: 5864497 (1999-01-01), Suh
patent: 5872736 (1999-02-01), Keeth

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