Memory architecture

Details Memory architecture Memory architecture

2002-09-19

2003-10-28

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S189090

Reexamination Certificate

active

06639824

ABSTRACT:

BACKGROUND OF THE INVENTION
Ferroelectric metal oxide ceramic materials such as lead zirconate titanate (PZT) have been investigated for use in ferroelectric semiconductor memory devices. Other types of ferroelectric material, such as Strontium-bismuth-tantalate (SBT) or lead-lanthanum-zirconium-titanate (PLZT) may also be used.
FIG. 1
shows a conventional ferroelectric memory cell
105
having a transistor
130
and a ferroelectric capacitor
140
. A capacitor electrode
142
is coupled to a plateline
170
and another capacitor electrode
141
is coupled to the transistor which selectively couples or decouples the capacitor from a bitline
160
, depending on the state (active or inactive) of a wordline
150
coupled to the transistor gate.
The ferroelectric memory stores information in the capacitor as remanent polarization. The logic value stored in the memory cell depends on the polarization of the ferroelectric capacitor. To change the polarization of the capacitor, a voltage which is greater than the switching voltage (coercive voltage) needs to be applied across its electrodes. An advantage of the ferroelectric capacitor is that it retains its polarization state after power is removed, resulting in a non-volatile memory cell.
FIG. 2
shows a plurality of memory cells arranged in a group
203
. Such types of memory architectures are described in, for example, Takashima et al., “High Density Chain ferroelectric random access Memory (chain FRAM)”, IEEEJrnl. of Solid State Circuits, vol.33, pp.787-792 (May 1998),which is herein incorporated by reference for all purposes. The group includes a plurality of memory cells, each comprising a transistor
230
coupled to a capacitor
240
in parallel, coupled in series. One end of the group is coupled to a bitline
250
while the other end is coupled to a plateline
270
. The gates of the transistors are coupled to respective wordlines
250
. The bitline is coupled to a sense amplifier circuit to facilitate memory accesses (e.g., reads and writes).
During standby or when the memory group is not selected for a memory access, the wordlines of the group are active to render the cell transistors of the group conductive. The capacitors of the group are shorted when transistors are conductive. To retrieve or read information from one memory cell of the group, a pulse (e.g., 2,5V) is provided at the plateline. The wordline corresponding to the row address of the memory access is deactivated, causing the transistor of the selected cell to be non-conductive. As a result, the pulse applies a potential across the capacitor of the selected cell. A signal corresponding to the information stored in capacitor is then placed on the bitline and sensed by a sense amplifier. The read access is destructive, requiring the signal sensed by the sense amplifier to be written back to the selected memory cell.
The present invention proposes an improved series memory architecture.
SUMMARY OF THE INVENTION
The invention relates generally to ICs in which memory cells are arranged in groups. In one embodiment, the memory cells comprise ferroelectric memory cells. A variable voltage generator (VVG) for generating an output voltage is provided. The VVG generates a different output voltage level based on the location of an addressed memory cell within the memory group to facilitate memory accesses.
In one embodiment, a plateline is coupled to a first end of the memory group. The plateline includes a plateline driver which is coupled to the VVG. The VVG provides the output voltage to the plateline during a read access, which provides a plateline pulse on the plateline. The magnitude of the plateline pulse depends on the location of the selected memory cell within the group.
A bitline coupled to a second end of the group. A sense amplifier, which includes write circuitry, is coupled to the bitline, the sense amplifier includes a write circuitry. In one embodiment, the VVG is coupled to the write circuitry to provide the output voltage to the write circuitry during a write access. The output voltage depends on the location of the accessed memory cell.
In an alternative embodiment, a VVG is coupled to both the sense amplifier and plateline driver to provide plateline voltages and write voltages having different voltage levels depending on the location of the accessed memory cell. Providing two separate VVG, one each for the sense amplifier and plateline driver is also useful. By providing different voltage levels for reads and/or writes, signal loss caused by capacitances which is dependent on the location of the memory cell within the group can be avoided. This improves read and/or write operations in series memory architectures.


REFERENCES:
patent: 5798966 (1998-08-01), Keeney
patent: 6459609 (2002-10-01), Du

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