Memory apparatus having a short word line cycle time and...

Details Memory apparatus having a short word line cycle time and... Memory apparatus having a short word line cycle time and...

2006-08-15

2006-08-15

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S222000

Reexamination Certificate

active

07092300

ABSTRACT:
Memory apparatus having a short word line cycle time and method for operating a memory apparatus. One embodiment provides a memory apparatus comprising at least one cell array having a multiplicity of memory cells, with each of the memory cells having an associated word line and an associated bit line; a control device which has a signaling connection to the word lines and to the bit lines and is configured to read data stored in the memory cells and to write data to the memory cells; wherein the control device is configured to execute a destructive read command (DRD) for reading data from at least one of the memory cells, comprising: electrically biasing a bit line associated with the at least one memory cell, opening a word line associated with the at least one memory cell, and destructively reading data stored in the at least one memory cell.

REFERENCES:
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patent: 6801980 (2004-10-01), Ji et al.
patent: 6879540 (2005-04-01), Maruyama et al.
patent: 6885591 (2005-04-01), Nong
patent: 2002/0161967 (2002-10-01), Kirihata et al.
patent: WO 2005/008674 (2005-01-01), None
German Examination Report dated Apr. 14, 2003.

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