Memory and method of reading out of the memory

Details Memory and method of reading out of the memory Memory and method of reading out of the memory

1995-05-02

1996-10-22

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Multiplexing

36523002, 36523003, 365233, 365236, 365239, G11C 700, G11C 800

Patent

active

055684270

ABSTRACT:
A memory and a method for reading out of memory including a register for holding one row of data of a memory cell array, a plurality of first switching transistors for switching ON/OFF between a plurality of bit lines and the corresponding bits in the register, a plurality of second switching transistors for switching ON/OFF between the bit lines and a pair of data bus lines and a plurality of third switching transistors for switching ON/OFF between the data bus lines and the bits in the register. In random access of memory cells, selection and control is performed for the plurality of second switching transistors with an output of a column decoder. In sequential reading out of the register, one row data of the memory cells selected by a row decoder are written in the register by controlling the plurality of first switching transistors and with an output of the column decoder, sequential selection and control of the plurality of third switching transistors is performed.

REFERENCES:
patent: 4847809 (1989-07-01), Suzuki
patent: 5051955 (1991-09-01), Kobayashi
patent: 5093808 (1992-03-01), Foss
patent: 5220527 (1993-06-01), Ohsawa
patent: 5241503 (1993-08-01), Cheng
patent: 5398209 (1995-03-01), Iwakiri et al.
patent: 5457657 (1995-10-01), Suh

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