Memory and circuit for accessing data bits in a memory array in

Static information storage and retrieval – Read/write circuit – Multiplexing

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365205, G11C 700

Patent

active

060976403

ABSTRACT:
A method and circuit for accessing data bits in a memory array in a multi-data rate operation. In one architecture, a memory device includes a memory array for storing data values, multiple (N) sensing circuits, multiple (K) control lines, and an I/O pad. One sensing circuit couples to each data value being retrieved from the memory device. The I/O pad operatively couples to the sensing circuits. And each control line couples to at least one sensing circuit and has a clock phase unique from remaining control lines.

REFERENCES:
patent: 5497347 (1996-03-01), Feng
patent: 5504875 (1996-04-01), Mills et al.
patent: 5537352 (1996-07-01), Meyer et al.
patent: 5748561 (1998-05-01), Hotta

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