Memory alignment system and method

Details Memory alignment system and method Memory alignment system and method

1984-07-10

1988-06-07

Shaw, Gareth D.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

G11C 500

Patent

active

047501545

ABSTRACT:
A memory alignment system and method are disclosed having a memory bus designed to accommodate more than one write instruction at a time and where data from different write instructions are merged together when the writes are destined for alignable locations in memory. In one embodiment, a write buffer and a comparator are configured to compare successive instructions for alignable destination addresses. In another embodiment, a content associative buffer is employed to compare the address of a write instruction with the addresses of all other stored write instructions. A variable scheduler to control the unloading of the buffer is also disclosed as is an apparatus for merging data read from memory with data awaiting transmission to memory to obtain the most up-to-date version.

REFERENCES:
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patent: 4388701 (1983-06-01), Aichelmann, Jr. et al.
patent: 4395764 (1983-07-01), Matsue
patent: 4418399 (1983-11-01), Sakurai
patent: 4433394 (1984-02-01), Torii et al.
patent: 4507731 (1985-03-01), Morrison
patent: 4532559 (1985-07-01), Long et al.
patent: 4561071 (1985-12-01), Hashimoto et al.
patent: 4602365 (1986-07-01), White et al.

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