Memory access system providing increased throughput rates...

Details Memory access system providing increased throughput rates... Memory access system providing increased throughput rates...

2007-04-03

2007-04-03

Peyton, Tammara (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S023000, C710S028000, C710S029000, C710S033000, C710S034000, C710S035000, C711S100000, C709S212000, C709S241000, C365S200000, C365S201000

Reexamination Certificate

active

10709234

ABSTRACT:
Enhancing the throughput rate of a memory access system by using store and forward buffers (SFB) in combination with a DMA engine. According to an aspect of the present invention, the worst case throughput rate (without use of SFBs) is computed, and maximization factor equaling a desired throughput rate divided by the worst case throughput rate is computed. A number of SFBs is determined as equaling one less than the maximization factor. By placing the SFBs at appropriate locations in the data transfer path, the desired throughput rate may be attained when transferring large volumes of data.

REFERENCES:
patent: 6678777 (2004-01-01), Rao et al.
Singhal, Rakshit et al.; A Novel Mechanism to Optimize Memory to Memory Data Transfers in a System-on-Chip Using Store and Forward Bridge and a DMA Engine; pp. 1-6.
Fact Sheet: AR7Wi Wireless ADSL Router; pp. 1-4; Texas Instruments Real World Signal Processing; 2004.
Parekhji, Nikita et al.; DFT For Test Optimisations in a Complex Mixed-Signal . . . ; 2004 IEEE ITC International Test Conference; pp. 773-782.

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