Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-07-18
2002-10-22
Peikari, B. James (Department: 2186)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189011, C365S191000, C710S035000
Reexamination Certificate
active
06469940
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory access method and system and, more particularly, to a memory access method and system for writing and reading with respect to a synchronous dynamic random access memory (SDRAM) and control thereof.
2. Description of Related Art
Generally, a dynamic random access memory (DRAM) with a simple information storage structure has a memory capacity larger than that of a static random access memory (SRAM)
However, upon random writing/reading access, as a ROW address and a COLUMN address are set in a time-multiplexing manner, the data transfer speed is low.
Accordingly, if a high data transfer speed is required, a synchronous type DRAM (SDRAM) which realizes high-speed access by pipeline processing is utilized. When accessing a page having the same ROW address, an access speed equivalent to that of SRAM can be attained.
However, since the SDRAM is based on the DRAM basic operation, if writing with the same ROW address changes to reading or if writing/reading to/from some page is made and then writing/reading is made to/from another page, there is a period where the data bus is not effectively used, and the data transfer efficiency is lowered.
Besides the lowered efficiency, another problem occurs in continuous random access systems. Specifically, waiting periods that occur upon access to a memory require the use of temporary storage elements, which complicates the design of the memory interface.
These problems will be described in more detail below.
FIG. 4
is a block diagram showing a well-known SDRAM (Synchronous DRAM). In this SDRAM, a command decoder
9
determines the type of command by a command signal d input to the memory device. If the command decoder
9
interprets the command as a “row address setting signal” (ACT), an input address c is latched.
However, if the command decoder
9
interprets the command as a “writing (WR)” or “reading (RD)” signal, the input address c is latched in the address buffer
2
, and then output to a COLUMN address decoder
7
.
Further, if the command decoder
9
interprets the command as a “mode setting” signal, the input address c is latched in the address buffer
2
, and then output to a mode register
8
.
A control signal generator
10
generates a control signal based on the setting of the mode register
8
to operate respective elements of the DRAM based on the condition of the mode register
8
, thus controlling the respective elements of the DRAM, i.e., the address buffer
2
, a burst counter
3
, the ROW address decoder
6
, the COLUMN address decoder
7
and a data controller
16
.
Parameters set in the mode register
8
include a burst length and a burst address reading order are set to determine the operation condition for the burst counter
3
.
After the power is turned on, the burst length and the burst address reading order are set through the address buffer
2
based on an address signal input a. The control signal generator
10
controls the burst counter
3
in accordance with the set burst length and the burst address reading order.
The burst counter
3
generates a series of addresses for the burst transfer from the input address in accordance with the burst length and the burst address reading order controlled by the control signal generator
10
, and outputs the series of addresses through the address buffer
2
to the ROW address decoder
6
.
The ROW address decoder
6
and the COLUMN address decoder
7
decode a ROW address and a COLUMN address respectively inputted from the address buffer
2
, and select a memory cell to/from which data is to be written or read, from a memory array
11
.
The control signal generator
10
controls the data controller
16
using the control signal generated from the input command of the command decoder
9
, to store input data e from a data input/output buffer
15
into the selected memory cell in the memory array
11
. Further, if the input command from the command decoder
9
is “reading”, the controller
16
reads information from the selected memory cell in memory array
11
, and outputs the information from the data input/output buffer
15
through a sense amplifier
12
.
The burst counter
3
generates a burst transfer address from the burst length and the burst address reading order set in the mode register
8
. The memory cell in the memory array
11
designated by the ROW address decoder
6
and the COLUMN address decoder
7
is selected from the ROW address and the COLUMN address. The data controller
16
is controlled by the control signal generated by the control signal generator
10
. If the command to the control signal generator
10
from the command decoder
9
is a “writing” signal, the data e inputted through the data input/output buffer
15
is stored into the selected memory cell in the memory array
11
.
On the other hand, if the command signal from the command decoder
9
is a “reading” signal, the information is read from the selected memory cell in memory array
11
, and output from the data input/output buffer
15
through the sense amplifier
12
.
FIG. 5
shows access timing in the above operation.
FIG. 5
shows an example of an access operation in which the burst length has a clock length of 8, and the COLUMN address strobe (CAS) latency has a clock length of 2. A combination of control signals for execution of processing is called a command. When processing is switched from writing to reading, data on the data bus (D) is stored into the memory when the writing (WR) command is set. On the other hand, when reading (RD) information from the memory, after the execution of command, the information is output to the data bus with a clock length delay of the CAS latency. Accordingly, a period where the data bus is not used exists between the writing processing and the reading processing.
In a situation where a ROW address is set (ACT) and writing (WR) or reading (RD) processing is performed using a different ROW address, precharging processing is performed to restore the idle status, and a new ROW address is set (ACT) and writing (WR) or reading (RD) is performed. Thus, a period exists where the data bus is not used during the writing or reading processing.
SUMMARY OF THE INVENTION
As described above, the present invention provides an SDRAM memory access method to reduce the idle period where a data bus is not used caused by accessing a memory area of a different ROW address, by reservation registration and preparation for the execution of command to be executed next during a burst data writing/reading cycle, so as to increase data transfer efficiency and realize high speed burst data transfer, and to provide a simple memory interface.
REFERENCES:
patent: 4748627 (1988-05-01), Ohsawa
patent: 5657269 (1997-08-01), Nanamiya
patent: 5813023 (1998-09-01), McLaury
patent: 5903509 (1999-05-01), Ryan et al.
patent: 6262938 (2001-07-01), Lee et al.
patent: 6339560 (2002-01-01), Naritake
patent: 10-233091 (1998-09-01), None
patent: 2000-187982 (2000-07-01), None
patent: 2000-231788 (2000-08-01), None
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