Memory access buffer and reordering apparatus using priorities

Details Memory access buffer and reordering apparatus using priorities Memory access buffer and reordering apparatus using priorities

1998-04-29

2000-11-07

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711 5, 711105, G06F 1202

Patent

active

061450650

ABSTRACT:
A current problem is that when a DRAM is to be accessed through a data bus, the DRAM is accessed independently of a bank, a row address, etc., and therefore, is inefficient. To solve this problem, an address bus and a data bus are connected to a main memory part independently of each other, a temporary memory part for holding a plurality of addresses in advance is disposed on the address bus side and holds addresses for every access to the main memory part regardless of transfer of data, thereby pipelining address inputting cycles. Further, for the purpose of an effective operation of the main memory part, using the addresses which are held, the addresses are rearranged in such a manner that addresses with the same row addresses become continuous to each other, or when there are not addresses with the same row addresses, addresses different banks from each other become continuous to each other, and the memory is thereafter accessed. This reduces the number of precharges, shortens a standby period which is necessary for a precharge, and realizes accessing while reducing a wasteful use of time.

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Japanese Search Report dated Sep. 1, 1998 in English and Japanese.
Kazushige Ayukawa, et al., "An Access-sequence Control Scheme to Enhance Random Access Performance of Embedded DRAMs," 1997 Symposium on VLSI Circuits Digest of Technical Papers, pp. 59-60.

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