Media access controller with power-save mode

Details Media access controller with power-save mode Media access controller with power-save mode

2006-09-22

2009-02-17

Knoll, Clifford H (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S306000, C710S240000, C713S300000

Reexamination Certificate

active

07493440

ABSTRACT:
There is provided a media access controller with a power-save mode. Particularly, the media access controller of the present invention minimizes power loss by disabling clocks applied to all blocks, including CPU, of the media access controller during the power-save mode. The media access controller of the present invention includes: a power-save master for securing stable transmission/reception of data through bus by respective processors contained in the controller; a wake-up timer for noticing that the power-save mode is expired; a power control unit for determining whether to supply a power to a phase-locked loop, and a timing when clocks for the media access controller are applied and disabled; and a locktime register for storing a locktime when an output of the phase-locked loop is settled. Additionally, there is provided a method of efficiently changing the media access controller from the active mode to the power-save mode, and vice versa.

REFERENCES:
patent: 6357013 (2002-03-01), Kelly et al.
patent: 6934870 (2005-08-01), Amos
patent: 7139937 (2006-11-01), Kilbourne et al.
patent: 2003/0167413 (2003-09-01), Stachura et al.
patent: 2003/0226050 (2003-12-01), Yik et al.
patent: 2004/0098530 (2004-05-01), Earl et al.
patent: 2004/0213289 (2004-10-01), Liu et al.

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