Mechanisms to prevent undesirable bus behavior

Details Mechanisms to prevent undesirable bus behavior Mechanisms to prevent undesirable bus behavior

2003-05-22

2009-08-18

Wilson, Yolanda L (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S044000, C710S015000, C710S017000, C710S018000

Reexamination Certificate

active

07577877

ABSTRACT:
A system includes proxy logic which detects situations which, unless action is taken, would result in undesirable bus behavior. In one embodiment, the target device of a bus cycle includes proxy logic which determines when the target device is unable to respond correctly to a bus cycle. In this situation, the proxy logic blocks a bus signal from being received by the addressed logic in the target device, thereby preventing the target device from responding at all. In another embodiment, proxy logic is located external to the target device and determines when the target device has not responded to a cycle intended for it. When this condition has occurred, the proxy logic responds to the cycle before the bus's subtractive decode agent has a chance to claim the cycle. The proxy logic's response may be to return bogus data or terminate or abort the cycle.

REFERENCES:
patent: 5712967 (1998-01-01), Grossman et al.
patent: 5815647 (1998-09-01), Buckland et al.
patent: 6000043 (1999-12-01), Abramson
patent: 6625761 (2003-09-01), Sartore et al.
patent: 2002/0194548 (2002-12-01), Tetreault
PCI Special Interest Group, “PCI Local Bus Specification,” Production Version, Revision 2.0, Apr. 30, 1993 (48 p., double-sided).

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