Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2006-06-27
2010-06-08
Connolly, Mark (Department: 2115)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S401000, C713S600000, C710S305000
Reexamination Certificate
active
07734944
ABSTRACT:
A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.
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Chen Jonathan Y.
Magee Jeffrey A.
Webber David A.
Bleit Gibbons Gutman Bongini & Bianco P.L.
Connolly Mark
Gibbons Jon A.
International Business Machines - Corporation
Marhoefer L. J.
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