Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2000-08-31
2003-10-21
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S166000
Reexamination Certificate
active
06636955
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a mechanism that reduces skew in data and clock signal timing between related source-synchronous data channels. More particularly, the invention relates to a memory controller that reduces skew between related skewed data channels. More particularly still, the invention relates to reducing skew between data channels and providing an automatic feature to initialize the logic used to reduce the skew.
2. Background of the Invention
Digital electronic systems, such as all types of computers, cellular telephones, DVD players, etc., have various technical issues that must be addressed when designing such systems. This disclosure focuses on one such issue-how to transmit digital data between two points within the system.
Digital signals are electrical signals whose voltage level at any point in time is either at one predetermined level or another (e.g., 3.3V and 0V). Information is encoded into a digital signal by way of the voltage levels and/or the sharp transitions (referred to as “edges”) between the voltage levels. Digital signals typically are synchronized to a clock signal. A clock signal is a periodic digital signal which repeatedly oscillates between two voltage levels. When transmitting digital data from a source point to a receiving point within a digital system, both the source device and the receiving device must use a clock signal to send and receive the data. Each clock signal is generated with some type of clock generating circuit, such as a crystal oscillator. Further, the source device and receiving device may generate their own clocks independently of each other. As such, although both devices may generate and use, for example, a 100 Megahertz (“MHz”) clock (i.e., 100 million cycles per second), the two clocks may not be synchronized. This means that the rising and falling edges of the two clocks do not coincide with respect to time.
Generally, there are two types of clocking schemes available to send data between devices in a digital system-receiver-synchronous clocking and source-synchronous clocking. In receiver-synchronous clocking, the source device uses its clock to transmit the data and the receiving device uses the receiver's clock to receive the data. That is, both devices use their own, unsynchronized clocks. The advantage of receiver-synchronous clocking is that a clock signal does not need to be transmitted along with the data, thereby saving a wire or signal trace on a printed circuit board. Additionally, once the transmitted data is clocked into an input buffer in the receiving device, the data is already in the clock “domain” of the receiving device (i.e., the data is synchronized to the clock of the receiving device). A disadvantage of receiver-synchronous clocking is that the circuitry needed to receive the transmitted data into an input buffer in the receiving device is relatively complex because the transmitted data is not already synchronized with the receiver's clock.
Source-synchronous clocking requires the source device to transmit its clock along with the data to the receiving device. The receiving device then uses the source's clock to latch in the transmitted data into the receiver's input buffer and uses the same clock signal to provide data back the source.
FIG. 1
conceptually illustrates source-synchronous clocking. As shown, a transmitter (“TX”)
20
provides data (designated as “write data”) to the receiver (“RX”)
24
. Along with the write data, the transmitter
20
sends its clock (“TX CLK”) to the receiver
24
, which the receiver uses to latch in the write data. The TX CLK is routed back to the transmitter conceptually as shown. When the receiver
24
needs to provide data back to the transmitter (“read data”), the receiver
24
uses the RX CLK, which originally was generated by the transmitter
20
, to place the read data on the bus back to the transmitter
20
.
Source-synchronous clocking enables the receiver to have a relatively simple input circuit to clock in the transmitted data, but disadvantageously requires an extra wire for the source's clock and, following receipt by the receiver, also requires the transmitted data to be synchronized by the receiver to the receiver's clock.
The present disclosure addresses issues that arise in a source-synchronous transmission scheme in a digital system. For example, referring to
FIG. 2
, a transmitter
20
may communicate data to three different receivers
26
,
28
, and
30
. As shown, each of the three receivers may be physically located a different distance from the transmitter. Because signals take a finite amount of time to propagate along a conductor, the RX CLK signals each receiver routes back to the transmitter may not be synchronized. That is, the TX CLK signals provided to each receiver are synchronized when they leave the transmitter
20
, but by the time those signals each follow their round trip path to and from their respective receiver, the signals are out of phase with respect to each other by the time they are received back at the transmitter
20
. This phase difference is referred to generally as “skew” and is a problem that must be addressed to synchronize data received from the three receivers. The problem of skewing has become increasingly a more significant problem as data rates have increased.
Some digital transmission systems use a “valid” signal that is transmitted along with data to a receiving device. The valid signal alerts the receiving device that valid data is present on the bus and should be latched in to the receiving device. Although a generally effective scheme, the valid signal requires a separate wire dedicated to the valid signal. A system may have many such valid signals. Valid signals-thus disadvantageously occupy valuable real estate on a printed circuit board that might be better used for other functionality.
Accordingly, there is a need to solve reduce or eliminate skew in multi-channel digital communication system. Further, such a solution should also be relatively easy to initialize and avoid, if possible, using a valid signal. Despite the advantages such a system would provide, to date no such system is known to exist.
BRIEF SUMMARY OF THE INVENTION
The problems noted above are solved in large part by a computer system having a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself.
Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. The skew is determined a priori and programmed into the system.
During system initialization, the pointers are synchronized. A predetermined bit pattern (e.g., all 1s) is written to each of the memory channels and then read back approximately simultaneously from the channels. Each channel's load pointer is held at 0 until the predetermined bit pattern is received on
Bannon Peter J.
Baum Allen J.
Bouchard Gregg A.
Breach Scott E.
Kessler Richard E.
Choi Woo H.
Hewlett--Packard Development Company, L.P.
Kim Matthew
LandOfFree
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