Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-09-18
2003-10-28
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S501000, C257S350000, C257S361000, C257S509000
Reexamination Certificate
active
06639295
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device which is suitable for use in a power converter, such as an inverter.
2. Description of the Background Art
FIG. 10
is a vertical section showing a semiconductor device according to a conventional example as a background of the present invention. This semiconductor device
151
is formed as a vertical n-channel IGBT. The semiconductor substrate
200
, a silicon substrate, comprises an n region
201
, a p collector region
202
, p base regions
203
, and n source regions
205
. These semiconductor regions
201
to
203
and
205
are formed by selectively introducing p-type and n-type impurities into the pair of main surfaces of the n-type substrate forming the n region
201
. In the n-type substrate, the region where the semiconductor regions
201
to
203
and
205
are absent corresponds to the n region
201
.
The p collector region
202
is formed selectively and exposed in the lower main surface of the semiconductor substrate
200
. The p base regions
203
are selectively formed and selectively exposed in the upper main surface of the semiconductor substrate
200
. The n source regions
205
, shallower than the p base regions
203
, are selectively formed inside the p base regions
203
and selectively exposed in the upper main surface of the semiconductor substrate
200
.
The semiconductor device
151
further comprises gate electrodes
206
, gate insulating films
207
, insulating films
208
, emitter electrodes
209
, and a collector electrode
211
. Each gate electrode
206
faces a channel region with the gate insulating film
207
interposed therebetween; the channel region is a part of the exposed surface of the p base region
203
that is interposed between the n region
201
and the n source regions
205
. Each emitter electrode
209
is connected to the exposed surface of the p base region
203
and the n source regions
205
in the upper main surface of the semiconductor substrate
200
. The insulating films
208
electrically insulate the gate electrodes
206
and the emitter electrodes
209
. The collector electrode
211
is connected to the lower main surface of the semiconductor substrate
200
where the p collector region
202
is exposed.
In the use of the semiconductor device
151
as IGBT, with a positive collector voltage, relative to the emitter electrodes
209
, applied to the collector electrode
211
(usually through a load), a gate voltage, relative to the emitter electrodes
209
, is applied to the gate electrodes
206
. When a positive gate voltage exceeding the threshold voltage is applied, an inversion layer is formed in the channel region, and electrons (the black dots in
FIG. 10
) are injected into the n region
201
and holes (the white dots in
FIG. 10
) are then injected from the p collector region
202
into the n region
201
. As a result, a phenomenon known as conductivity modulation takes place in the n region
201
, which causes the collector electrode
211
and the emitter electrodes
209
to become conductive to each other at a low on-state voltage. When the gate voltage is reduced below the threshold voltage (usually zero or negative value), the inversion layer formed in the channel region disappears and the collector electrode
211
and the emitter electrodes
209
are thus cut off.
As described above, the semiconductor device
151
as IGBT is a switching element advantageous because of its low on-state voltage and voltage controllability; however, unlike MOSFET, it does not contain a diode. Accordingly, when used in a power converter like an inverter, the semiconductor device
151
requires a free-wheeling diode provided outside. This produces the problem that the inductance of the interconnection hinders high-speed switching, and also makes the manufacturing process complicated and causes the applied equipment, such as a power converter, to be large-sized.
To solve these problems, Japanese Patent Application Laid-Open No.5-152574(1993) (which is hereinafter referred to as a first reference) discloses a semiconductor device in which semiconductor regions belonging to the IGBT and semiconductor regions belonging to the free-wheeling diode are disposed in different portions in a single semiconductor substrate.
FIG. 11
shows a vertical sectional structure of a semiconductor device
152
and
FIG. 12
shows a vertical sectional structure of a semiconductor device
153
, both of which are disclosed in the first reference.
Each of the semiconductor devices
152
and
153
has a vertical n-channel IGBT and a vertical diode which are connected in anti-parallel to each other, where a plurality of semiconductor regions belonging to the IGBT and the diode are fabricated in a single semiconductor substrate
200
. The semiconductor substrate
200
, a silicon substrate, has an IGBT region
220
and a diode region
221
selectively defined in different regions along the pair of main surfaces. An anti-interference region
223
is provided between the IGBT region
220
and the diode region
221
as a region for suppressing interference between them.
The semiconductor substrate
200
has, in the IGBT region
220
, part of the n region
201
that belongs to the IGBT, the p collector region
202
, p base regions
203
, and n source regions
205
. The semiconductor substrate
200
also has, in the diode region
221
, part of the n region
201
that belongs to the diode, an n
+
region
241
, and an anode region
204
. The n region
201
functions as an n base region in the IGBT region
220
and as a cathode region in the diode region
221
. The semiconductor device
152
further has p
+
regions
240
and n
+
regions
241
selectively formed in the IGBT region
220
and the anti-interference region
223
. The semiconductor device
153
has p regions
230
selectively formed in the anti-interference region
223
.
On the upper main surface of the semiconductor substrate
200
, an anode electrode
210
is connected to the exposed surface of the anode region
204
. A cathode electrode
212
is connected to the part of the lower main surface of the semiconductor substrate
200
which belongs to the diode region
221
. The emitter electrodes
209
and the anode electrode
210
are connected to each other and the collector electrode
211
and the cathode electrode
212
are integrally coupled.
As described above, the semiconductor devices
152
and
153
each comprise an IGBT and a diode, where the diode connected in anti-parallel to the IGBT functions as a free-wheeling diode associated with the IGBT. Therefore, when the semiconductor device
152
or
153
is applied to a power converter such as an inverter, it is possible, in the assembly of the power converter, to remove the process of separately preparing the IGBT and the free-wheeling diode as separate semiconductor chips and connecting them with interconnection. This also makes the power converter compact. Moreover, since it is not necessary to connect the IGBT and the free-wheeling diode with interconnection, the problem that the switching speed is reduced by the interconnection inductance can be avoided to realize high speed switching.
However, the semiconductor devices
152
and
153
are disadvantageous in that they need the anti-interference region
223
to prevent interference between the IGBT and the diode. The interference between the IGBT and the diode means the phenomenon in which the reverse recovery current generated when the diode performs reverse recovery operation flows from the diode region
221
into the IGBT region
220
to cause a parasitic thyristor in the IGBT to conduct. Preventing the interference requires securing sufficiently large width L for the anti-interference region
223
. Therefore the semiconductor devices
152
and
153
require larger area for the semiconductor substrate
200
, or larger chip size.
SUMMARY OF THE INVENTION
The present invention has been made to solve the aforementioned problems of the conventional technique, and an object
Hatae Shinji
Majumdar Gourab
Yamamoto Akihisa
Fenty Jesse A
Lee Eddie
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