Mechanism for high bandwidth DMA transfers in a PCI environment

Details Mechanism for high bandwidth DMA transfers in a PCI environment Mechanism for high bandwidth DMA transfers in a PCI environment

1998-10-13

1999-10-19

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710113, 710117, 710124, 710127, G06F 1300

Patent

active

059681535

ABSTRACT:
A method and apparatus for maximizing the performance of DMA transfers over a PCI.TM. bus are provided which includes a Per-Channel Retry count, Double Buffer Management, Wait Enable functionality, Back Up register functionality, Gather/Scatter mapping, a method for minimization of PIO writes, Read Semaphore functionality, a method for servicing of DMA transfers during FMU latency periods, Valid bit functionality, high and low water thresholds, and re-usable page tables.

REFERENCES:
patent: 5664226 (1997-09-01), Czako et al.
patent: 5729705 (1998-03-01), Weber
patent: 5734848 (1998-03-01), Gates et al.
patent: 5734867 (1998-03-01), Clanton et al.
patent: 5748944 (1998-05-01), Ng
patent: 5748945 (1998-05-01), Ng

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