Mechanical strength die sorting

Details Mechanical strength die sorting Mechanical strength die sorting

1998-10-29

2001-04-24

Walsh, Donald P. (Department: 3653)

Classifying, separating, and assorting solids

Sorting special items, and certain methods and apparatus for...

Condition responsive means controls separating means

C209S599000, C209S938000, C382S145000

Reexamination Certificate

active

06222145

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor chip manufacture and a method and apparatus for detecting physical strength of semiconductor chips.
BACKGROUND OF THE INVENTION
The production of semiconductor devices may be considered to include a plurality of stages. Each stage may include one or more steps from the provision of a semiconductor substrate to the final mounting of an individual semiconductor chip onto a carrier and subsequent incorporation of the carrier into a larger device. The production process may be thought of as roughly involving four stages.
In the first stage, which may be identified as front end of line (FEOL), processes are carried out on a semiconductor substrate. Such a substrate is typically silicon. However, other substrates, such as silicon carbide, or other crystalline or amorphous materials may be utilized as a substrate.
Front end of line processing may including implanting into or depositing onto the semiconductor substrate dopants and/or other materials. The semiconductor substrate may also be heat treated. Typically, FEOL processes may be thought of as generating many individual logic gates, memory cells, and/or other discrete circuit elements on and/or over the surface of the semiconductor substrate.
The second stage of semiconductor device manufacture may be referred to as “back end of line” (BEOL) processes. BEOL processes may include depositing one or more layers of one or more conductors and/or insulators onto the wafer and the structures created during the FEOL processing to form three-dimensional structures interconnecting individual elements in and/or on the semiconductor substrate. BEOL processes typically may be thought of as creating very large scale integrated (VLSI) circuits patterned in an array over the semiconductor substrate as individual devices. Typically, the array of VLSI circuits is rectangular.
After BEOL processing, VLSI devices typically are probed and/or tested for speed and/or quality. A map of the electrical performance of devices and/or circuits on the wafer may also be generated as part of BEOL processing.
Typically, a plurality of chips are created on one semiconductor substrate. After BEOL processing, the semiconductor substrate typically is subjected to processes under the general heading of dice, sort, and pick (DSP). DSP processes typically involve separating individual devices, commonly referred to as “dice” (plural of “die”) or chips, from each other. The individual devices typically are separated by somehow cutting or sawing the semiconductor substrate. The semiconductor substrate may be provided with intervening scribe lines between the individual devices.
During dicing, the overall semiconductor substrate may be supported by a support structure. The support structure may include an adhesive or other means to immobilize the individual chips during and/or after separation from the other chips and/or other portions of the semiconductor substrate. After cutting or otherwise separating the individual devices, each individual device may be picked up from the support structure. The picking of the devices may be controlled according to a performance map generated during the BEOL processing stage.
After cutting or otherwise separating the individual devices from the overall semiconductor substrate, the individual devices may be placed in containers suitable for packaging operations.
The production of semiconductor devices may also include a fifth stage that typically takes place after BEOL processing. According to the fifth stage, the semiconductor substrate and/or individual chips may undergo a back-side grind (BSG) operation. During BSG processing, semiconductor wafers may be ground on the back or non-device side.
The grinding may be carried out utilizing any suitable physical grinding means. For example, a grinding wheel may be used to grind the back-side of the semiconductor wafer to result in a wafer of a desired thickness. The back-side surface finish of the semiconductor wafer may also be controlled during the BSG processes. However, it is not necessary that the semiconductor wafer or chips be subjected to BSG processing.
After the DSP stage of processing, the individual separated semiconductor chips may be subjected to packaging (PKG) operations. Typically, PKG processing involves mounting an individual chip onto a larger carrier. Electrical connections may then be made between the chip and the electrical circuitry of the carrier. Then, the chip and carrier may be sealed or encapsulated in a suitable material or housing. After sealing, the chip and chip carrier may be electrically or mechanically tested.
SUMMARY OF THE INVENTION
Aspects of the present invention provide a method for sorting integrated circuit chips after separation from other chips. The method includes detecting at least one physical defect in the semiconductor chips and sorting the semiconductor chips into more than one acceptable classification based upon the physical defect.
The present invention also provides a device for sorting integrated circuit chips. The device includes a detector for detecting at least one physical defect in the semiconductor chips. A sorter sorts the semiconductor chips into more than one acceptable classification based upon the physical defect.
Further aspects of the present invention provide a method for forming an electronic package including a semiconductor chip and a semiconductor chip carrier. The method includes creating a plurality of semiconductor chips on a substrate. The individual semiconductor chips are separated from each other and/or from other portions of the substrate. At least one physical defect is detected in the semiconductor chips. The separated semiconductor chips are sorted based upon the physical defect. The semiconductor chips are mounted onto a carrier.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.


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