Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-05-30
2003-11-04
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S758000
Reexamination Certificate
active
06643814
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to methods and apparatus for implementing Maximum Transition Run (MTR) coding schemes, and to corresponding decoding systems.
BACKGROUND TO THE INVENTION
Channel codes, whereby input data bits are mapped to channel bits by a coding process, are commonly used to improve the characteristics of the bit-stream supplied to a recording channel. The code rate for such a code is usually specified as M/N and indicates the ratio of the number of data bits M to channel bits N. MTR codes are a particular type of channel code used to improve the characteristics of data to be supplied to a magnetic recording channel wherein the data is recorded on a magnetic recording medium such as a magnetic disk or tape. With air MTR codes the number of consecutive transitions that can occur in the magnetization pattern on the recording medium is limited to a particular number denoted by “j”. Thus, when used in conjunction with the NRZI (Non-Return-to-Zero-Inversion) recording format where “1” represents a magnetic transition and “0” no transition, an MTR code limits the maximum number of consecutive 1's at the NRZI encoder input. This j constraint has the desirable consequence of reducing errors in data recovery. More particularly, the bit-error rate performance is improved by providing a distance gain, i.e. an increase in the minimum Euclidean distance between recording patterns, or by eliminating likely error events, thus reducing the likelihood of errors in sequence detectors on the data recovery side. For example, when used in conjunction with higher-order partial response shaping and maximum likelihood sequence detection such as in an E2PR4 partial response channel, MTR codes with j=2 can deliver a distance gain of 2.2 dB. MTR codes with j=2 are also write-friendly, allowing user data to be written to a disk at very high data rates. High code-rate MTR codes are therefore of great interest, and particularly so for the higher-order partial response channels used in disk drives for example. Particular examples of MTR codes and encoding/decoding systems are disclosed in European patent application no. 99113399.2, assigned to the Assignee of the present application, and the prior art discussed in the introduction thereof.
Run Length Limited (RLL) codes are another type of channel code commonly used in magnetic recording. These codes impose a (G, I) constraint on the recorded data sequence, where “G” denotes the maximum number of consecutive 0's in the bit stream and “1” denotes the maximum number of consecutive 0's in the odd and even interleaved bit streams. IEEE Transactions on Magnetics, vol. 34, pp. 2382-2386, July 1998, “A New Target Response with Parity Coding for High Density Magnetic Recording Channels”, proposes a parity-based coding scheme in which a single parity bit is appended to RLL encoded data to allow detection of the dominant error events for a particular detector target. The proposed detection system is based on a Viterbi detector matched to the channel response which outputs estimates of the recorded code words, and a post-processor which correlates noise estimates with the dominant error events to indicate the type and position of the most-likely error event where the parity constraint is violated by an estimated code word.
As discussed further below, particular decoder systems embodying the present invention employ Noise Predictive Maximum Likelihood (NPML) detectors in conjunction with parity-based post processors. NPML, or “fractional target”, detection with finite impulse response (FIR) or infinite impulse response (IIR) targets is disclosed in International patent applications no's. WO 97/11544 and WO 98/52330 respectively, both assigned to the Assignee of the present application. Further, noise predictive post-processor designs for RLL encoded data are disclosed in the following: U.S. Pat. No. 5,949,831; International patent application no. PCT/US99/19910; and U.S. patent application Ser. No. 09/517,352, all assigned to the Assignee of the present application. In these cases, the post-processing schemes utilize IIR prediction/whitening filters and the error event detection mechanism is threshold based. Also as discussed below, particular encoder systems embodying the invention utilize a partial response precoder which operates on parity-coded data. U.S. Pat. No. 5,809,081 discloses systems in which an encoder adds one or two bits to an input word to generate a code string for supply to a precoder such that the precoded string has a preselected parity structure. U.S. Pat. No. 5,809,080 discloses a noise predictive Viterbi detector for such a system, the detector using a combined encoder parity and partial response trellis.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided a method for encoding a succession of M-bit data words to produce a succession of N-bit code words, where N>M, for supply to a magnetic recording channel, the method comprising the steps of:
encoding each M-bit data word in accordance with an MTR coding scheme to produce a G-bit word, where N>G>M, such that the maximum number of consecutive bits of a first value in a succession of said G-bit words is limited to a first predetermined value j
1
; and encoding said G-bit word to produce a said N-bit word in accordance with a second coding scheme wherein at least one parity bit, dependent on the bit-values of said G-bit word, is generated, such that the N-bit word satisfies a predetermined parity condition, and wherein bits of said first value in the G-bit word are mapped to respective bits of the N-bit word which are each of different value to the immediately preceding bit in the N-bit word;
wherein the second coding scheme is such that, in a succession of said N-bit words, the maximum number of consecutive bits which are each of different value to the immediately preceding bit is limited to a second predetermined value j
2
.
In methods embodying the present invention, therefore, M-bit data words are first encoded according to an MTR encoding scheme to produce G-bit words satisfying an MTR j=j
1
constraint. Thus, in a succession of these G-bit words, the maximum number of consecutive bits of a first value (which value corresponds to a transition in the eventual channel magnetization pattern) is limited to j
1
. (As will be appreciated, in embodiments conforming to the convention for MTR codes, the said bits of a first value will be bits of value “1”). Each G-bit word is then encoded to produce an N-bit word in accordance with a second coding scheme wherein one or more parity bits is generated, and bits of said first value in the G-bit word are mapped to respective bits of the N-bit word which are each of a different value to the immediately preceding bit of the N-bit word. Thus, bits of said first value are effectively mapped to bit-value transitions in the N-bit words, and hence to transitions in the magnetization pattern corresponding to the N-bit code words which is obtained on recording. The second coding scheme is implemented such that the maximum number of consecutive bit-value transitions in the output N-bit code words is limited to a predetermined value j
2
. The second coding scheme therefore results in a succession of N-bit words which satisfy an MTR j=j
2
constraint as well as a predetermined parity condition. Thus, in contrast to mere appending of a single parity bit to an RLL code as in the prior proposal referenced above, in embodiments of the present invention an MTR coding scheme is employed in the first encoding stage, and the second encoding stage, which involves the parity coding, is performed in such a manner that the resulting N-bit word still satisfies an MTR j constraint. As will be demonstrated by the particular examples described below, such encoding methods allow substantial performance gains to be achieved over both conventional MTR codes and RLL codes combined with a single parity bit. Moreover, while in general one or more pa
Cideciyan Roy D.
Coker Jonathan D.
Eleftheriou Evangelos S.
Galbraith Richard L.
Stanek Dave James
McConnell Daniel E.
Ton David
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