Material deposition method for integrated circuit manufacturing

Details Material deposition method for integrated circuit manufacturing Material deposition method for integrated circuit manufacturing

1991-08-23

1992-12-15

Nguyen, Nam X.

Chemistry: electrical and wave energy

Processes and products

Coating, forming or etching by sputtering

20419217, 20429811, C23C 1434

Patent

active

051714124

ABSTRACT:
The improved material deposition process of the present invention utilizes a first, low temperature deposition step followed by a second, high temperature/high power deposition step. In the first deposition step a collimation plate is placed between the sputtering target and the substrate, such that a collimated stream of sputtered material is deposited upon the substrate. The collimated stream provides a seed layer which aids in eliminating voids by partially filling the holes and grooves in the surface of the substrate. The second deposition step is conducted as a high temperature sputtering deposition. At the high temperature the sputtered material joins and flows with the seed layer, whereby the holes and grooves are more easily filled without voids and an improved planarized layer is achieved.

REFERENCES:
patent: 4724060 (1988-02-01), Sakata et al.
patent: 4756810 (1988-07-01), Lamont, Jr. et al.
patent: 4765815 (1988-07-01), Turner et al.
patent: 4816126 (1989-03-01), Kamoshida et al.
patent: 4824544 (1989-04-01), Mikalesen et al.
patent: 4851101 (1989-07-01), Hutchinson
patent: 4994162 (1991-02-01), Armstrong et al.

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