Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2001-05-02
2002-08-27
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S303000, C438S595000, C438S597000, C438S778000, C438S231000
Reexamination Certificate
active
06440875
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming spacer layers within microelectronic fabrications. More particularly, the present invention relates to method for forming, with enhanced linewidth control, spacer layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
Common in the art of microelectronic fabrication for use when fabricating microelectronic fabrication structures when fabricating microelectronic fabrications, and in particular for use when fabricating field effect transistor (FET) device structures when fabricating semiconductor integrated circuit microelectronic fabrications, is the use of spacer layers. Spacer layers are desirable in the art of microelectronic fabrication for use when fabricating microelectronic fabrication structures when fabricating microelectronic fabrications insofar as spacer layers, and in particular as employed adjacent gate electrodes within field effect transistor (FET) device structures within semiconductor integrated circuit microelectronic fabrications, allow for proper placement of additional microelectronic structures which are employed when fabricating microelectronic fabrications.
While spacer layers are thus desirable in the art of microelectronic fabrication and clearly often essential in the art of microelectronic fabrication, spacer layers are nonetheless not entirely without problems in the art of microelectronic fabrication.
In that regard, it is often difficult within the art of microelectronic fabrication to form within microelectronic fabrications spacer layers with optimal dimensional control, insofar as spacer layers are generally formed within microelectronic fabrications while employing etching methods which in turn provide spacer layers with substantial dimensional dependence upon etch parameters.
It is thus desirable in the art of microelectronic fabrication to provide methods and materials through which there may be formed within microelectronic fabrications spacer layers with enhanced dimensional control.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic fabrication, for forming spacer layers with desirable properties in the art of microelectronic fabrication.
Included among the methods, but not limited among the methods, are methods disclosed within: (1) Chen et al., in U.S. Pat. No. 5,573,965 (a method for forming, with attenuated etching degradation, a silicon oxide spacer layer adjoining a gate electrode within a field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication, by employing when forming a conformal silicon oxide layer from which is formed the silicon oxide spacer layer a thermal growth method followed by a deposition method in turn followed by an additional thermal growth method); (2) Ramaswami, in U.S. Pat. No. 5,783,475 (a method for forming, with attenuated silicon semiconductor substrate etching, a spacer layer adjacent a gate electrode within a field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication, by employing a series of three conformal dielectric layers formed successively upon the gate electrode and successively anisotropically and isotropically removing portions therefrom); and (3) Chien et al., in U.S. Pat. No. 6,069,042 (a method for forming, with enhanced dimensional control, a spacer layer adjacent a floating gate within a split gate field effect transistor (FET) device within a semiconductor integrated circuit microelectronic fabrication, by employing, in part, a bi-layer dielectric layer which is anisotropically etched to form the spacer layer).
Desirable in the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic fabrication, are additional methods and materials which may be employed for forming within microelectronic fabrications spacer layers with enhanced dimensional control.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming within a microelectronic fabrication a spacer layer.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the spacer layer is formed with enhanced dimensional control.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention there is provided by the present invention a method for forming within a microelectronic fabrication a spacer layer.
To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a topographic feature. There is then formed conformally over the topographic feature a second microelectronic layer formed of a second material and having a second thickness. There is then formed conformally upon the second microelectronic layer a first microelectronic layer formed of a first material and having a first thickness. Within the present invention, the first mater al serves as an etch stop with respect to the second material and the first thickness is less than the second thickness. There is then etched, while employing a first anisotropic etch method, the first microelectronic layer to form a spacer mask layer upon the second microelectronic layer. Finally, there is then etched, while employing a second anisotropic etch method selective to the second material, the second microelectronic layer to form a spacer layer while employing the spacer mask layer as an etch mask layer.
There is provided by the present invention a method for forming within a microelectronic fabrication a spacer layer, wherein the spacer layer is formed with enhanced dimensional control.
The present invention realizes the foregoing object by employing when forming a spacer layer from a blanket second microelectronic layer formed of a second material and having a second thickness formed conformally over a topographic feature formed over a substrate employed within a microelectronic fabrication a first microelectronic layer formed of a first material and having a first thickness formed conformally upon the second microelectronic layer. Within the present invention, the first material serves as an etch stop with respect to the second material and the first thickness is less than the second thickness. Since the first thickness is less than the second thickness, a spacer mask layer formed incident to anisotropic etching of the first microelectronic layer is formed with enhanced dimensional control, and since the spacer mask layer is employed in a self aligned fashion when forming a spacer layer from the second microelectronic layer, the spacer layer is thus also formed with enhanced dimensional control.
The method of the present invention is readily commercially implemented. The present invention employs methods and materials as are generally known in the art of microelectronic fabrication, but employed within the context of specific process limitations to provide a method for forming a spacer layer in accord with the present invention. Since it is thus at least in part a series of process limitations which provides the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.
REFERENCES:
patent: 5573965 (1996-11-01), Chen et al.
patent: 5783475 (1998-07-01), Ramaswami
pate
Chan Bor-Wen
Kuo Mei-Ru
Elms Richard
Luhrs Michael K.
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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