Masking error detection/correction latency in multilevel...

Details Masking error detection/correction latency in multilevel... Masking error detection/correction latency in multilevel...

2005-03-29

2005-03-29

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

06874116

ABSTRACT:
A method, and a corresponding apparatus, mask error detection and correction latency during multilevel cache transfers. The method includes the steps of transferring error protection encoded data lines from a first cache, checking the error protection encoded data lines for errors, wherein the checking is completed after the transferring begins, receiving the error protection encoded data lines in a second cache, and upon detecting an error in a data line, preventing further transfer of the data line from the second cache.

REFERENCES:
patent: 5604753 (1997-02-01), Bauer et al.
patent: 5629950 (1997-05-01), Godiwala et al.
patent: 5859999 (1999-01-01), Morris et al.
patent: 5860017 (1999-01-01), Sharangpani et al.
patent: 6161208 (2000-12-01), Dutton et al.
patent: 6502218 (2002-12-01), George et al.
Wolfe, A., “Patents shed light on Merced's Innards”, Electronic Engineering Times, Feb. 15, 1999.

Affiliated with

Also associated with

Rating

Masking error detection/correction latency in multilevel... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Masking error detection/correction latency in multilevel..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Masking error detection/correction latency in multilevel... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3457513