Mask ROM, and fabrication method thereof

Details Mask ROM, and fabrication method thereof Mask ROM, and fabrication method thereof

2006-01-24

2006-01-24

Jackson, Jerome (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S128000, C438S129000, C438S130000, C438S278000, C438S290000

Reexamination Certificate

active

06989307

ABSTRACT:
The present invention discloses a mask ROM which has excellent compatibility with a logic process and improves integration of a memory cell, and a fabrication method thereof. The mask ROM includes: a substrate where a memory cell array region and a segment select region are defined; first and second trenches respectively formed at the outer portion of the memory cell array region and at the outer portion of a buried layer formation region of the segment select region; an element isolating film and an isolating pattern respectively filling up the first and second trenches; a plurality of buried layers aligned on the substrate in a first direction by a predetermined interval, and surrounded by the isolating pattern; and a plurality of gates aligned in a second direction to cross the buried layers in an orthogonal direction.

REFERENCES:
patent: 5480822 (1996-01-01), Hsue et al.
patent: 6034403 (2000-03-01), Wu
patent: 6057195 (2000-05-01), Wu
patent: 6087699 (2000-07-01), Wann et al.
patent: 6414346 (2002-07-01), Kanamori
patent: 6429494 (2002-08-01), Zimmermann
patent: 6569735 (2003-05-01), Su

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