Mask for asymmetrical transistor formation with paired...

Details Mask for asymmetrical transistor formation with paired... Mask for asymmetrical transistor formation with paired...

1998-11-06

2001-03-13

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S286000, C438S291000, C438S305000

Reexamination Certificate

active

06200862

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the fabrication of semiconductor integrated circuits and, more particularly, to the fabrication of insulated gate, field effect transistor (IGFET) devices.
2. Description of the Related Art
An insulated-gate field; effect transistor (IGFET) device
5
, such as a metal-oxide semiconductor field-effect transistor (MOSFET) is shown in
FIG. 1. A
substrate
10
has a doped well region
12
, a p-doped well region will be used for purposes of illustration, formed therein. The substrate
10
has a p-doped channel region
14
that provides a conducting path between the n-doped source/drain region
16
A,
16
B and the n-doped source/drain region
18
A,
18
B. The addition, an p-doped punch-through region
20
is provided below the channel region
14
. Also formed in the substrate
10
are the isolation structures
22
and
24
. The gate structure of the IGFET device
5
includes an gate dielectric layer, directly over the channel region
14
, and a gate electrode
28
over the gate dielectric
26
. The gate structure
26
,
28
can include spacers
30
,
32
formed against the walls of the gate structure
26
,
28
. An insulating layer
34
covers the substrate
10
and the gate structure
26
,
28
. The insulating layer
34
has vias formed therein and the vias are filled with a conducting material. The conducting material provides conducting vias
36
to source/drain (electrode) regions
16
A,
16
B and
18
A,
18
B and to the gate electrode
28
. An insulating layer
38
, formed over insulating layer
34
, is patterned and the portions of the layer
38
that have been removed are filled with conducting material to provide conducting paths
40
. The conducting paths
40
and the remaining insulating material
38
are the interconnect layer
38
,
40
, the interconnect layer providing the electrical coupling between the IGFET device
5
and the remainder of the integrated circuit.
The operation of the IGFET device
5
can be understood as follows. A voltage applied to the gate electrode
28
causes a transverse field in the channel region
14
. The transverse field controls (e.g., modulates) the current flow between source/drain region
16
A,
16
B and source/drain region
18
A,
18
B. The punch-through region
20
is formed to prevent parasitic effects that can occur when this region is not formed in the device
5
. The spacers
30
,
32
and the dual-structured, doped source/drain regions
16
A,
16
B and
18
A,
18
B address a problem generally referred to as the “hot-carrier” effect. When only one source/drain region
16
A and
18
A is present and is formed by doping technique aligned with the electrode structure
26
,
28
, charge carriers from these regions can migrate into the channel region
14
and be trapped by the gate dielectric
26
. These trapped charge carriers adversely effect the transverse electric field normally formed in the channel region
14
by a voltage applied to the gate electrode
28
. The problem is alleviated by lightly-doping source/drain regions
16
A and
18
A by a technique that aligns this doping procedure with the gate structure
26
,
28
. Spacers
30
and
32
are next formed on the walls of the gate structure
26
,
28
. Source/drain regions
16
B and
18
B are formed by a doping procedure, resulting in source/drain doping concentrations at normal levels, that aligns the source/drain regions
16
B and
18
B with the spacers
30
and
32
, respectively. (While this two level doping procedure effectively eliminates the “hot-carrier” problem, the resistance between the two source/drain dual regions
16
A,
16
B and
18
A,
18
B is increased.) The isolation structures
22
,
24
provide electrical insulation the between the device
5
and other areas of the integrated circuit.
The use of the lightly-doped regions between the normally doped source/drain regions and the channel region provides relief from the “hot-carrier” effects, but the use of lightly-doped source/drain regions results in a higher effective resistance between the source/drain region and the channel region. This higher resistance results in a compromise of the operation of the device.
SUMMARY OF THE INVENTION
A need has therefore been felt for an IGFET device and technique for fabrication thereof having a feature of reducing the effects of “hot-carriers” effects. An additional desirable feature for such an IGFET device is that the resistance between the source/region electrode and the carrier region, that would normally result from the presence of lightly-doped source/drain regions, be reduced. A still further feature of the present invention is that, for a plurality of series-connected IGFET devices, only the source/drain terminal functioning as a drain of the IGFET device not connected to other device or devices in the series of devices has a lightly-doped source/drain terminal formed therewith.
The aforementioned and other features are accomplished, according to the present invention, by providing lightly-doped regions in the source/drain electrodes of selected IGFET devices, i.e., only for the electrodes of IGFET devices that function as drain electrode. A plurality of IGFET devices having device pairs each sharing a common source/drain region have asymmetricall) doped source/drain regions formed by lightly-doping both source/drain regions associated with a gate structure of an IGFET device. A patterned photoresist mask is formed that extends out from the gate structure only over one of the source/drain regions. Normally-doped source drain regions are then formed by ion implantation. A first type of normally-doped source/drain region is formed when the implanted ions are aligned by the gate structure. A second normally-doped source/drain region is aligned by the photoresist mask, the photoresist mask extending from the gate structure over a portion of the substrate. This second source/drain region is separated from the channel region by a lightly-doped source/drain region portion. This asymmetrically-doped IGFET device, i.e., with a first source/drain region being normally-doped and a second source/drain region having a normally-doped and a lightly-doped component, can be used when the second source/drain region functions as a drain electrode for the IGFET device in a plurality of coupled devices, wherein each pair of devices shares a common source/drain region. In a second embodiment, when a plurality of IGFET devices are connected in series, i.e., each device in the series sharing a common source/drain region, only the source/drain region not connected to another device in the series and functioning as a drain terminal is provided with the lightly doped source/drain region.


REFERENCES:
patent: 4992389 (1991-02-01), Ogura et al.
patent: 5286664 (1994-02-01), Horiuchi
patent: 5541436 (1996-07-01), Kwong et al.
patent: 5547888 (1996-08-01), Yamazaki
patent: 5674788 (1997-10-01), Wristers et al.
patent: 5759897 (1998-06-01), Kadosh et al.
patent: 5828104 (1998-10-01), Mizushima
patent: 5874340 (1999-02-01), Gardner et al.
Stanley Wolf, “Silicon Processing For The VLSI Era, vol. 2: Process Integration,” Lattice Press, California, 1990, pp. 348-360, 436-440.
Stanley Wolf, “Silicon Processing For The VLSI Era, vol. 3: The Submicron MOSFET,” Lattice Press, California, 1995, pp. 612-620.

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