Manufacturing process of semiconductor devices

Details Manufacturing process of semiconductor devices Manufacturing process of semiconductor devices

2001-06-05

2002-05-28

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

Fluid growth from liquid combined with preceding diverse...

C438S478000, C438S166000, C438S753000

Reexamination Certificate

active

06395622

ABSTRACT:

FIELD OF THE INVENTION
The present invention is relating to a manufacturing process of semiconductor devices, particularly to a manufacturing process of flip-chip-typed semiconductor devices, wherein the semiconductor devices have fuses connecting to the redundancy circuits.
BACKGROUND OF THE INVENTION
Conventionally the manufacturing process of semiconductor chip is shown in the
FIG. 1
mainly comprises providing the wafer
11
, wafer sort (
1
)
12
(pre-laser testing), laser repairing
13
, wafer sort (
2
)
131
(post-laser testing), dicing
14
, packaging
15
, final testing (
1
)
16
, bum-in
17
and final testing (
2
)
18
, etc. Wherein providing the wafer
11
, wafer sort (
1
)
12
, laser repairing
13
, wafer sort (
2
)
131
and dicing
14
are completed at a front section of the integrated circuit forming factory such as the foundry manufacturer, then packaging
15
, final testing (
1
)
16
, burn-in
17
and final testing (
2
)
18
are executed at a rear section of the packaging and testing factory.
At the front section of the integrated circuit forming factory, at first is to provide a wafer
11
and form a plurality of chips in the wafer (called integrated circuit layout). Thereafter “testing”
12
is to examine good chips, repairable bad chips and non-repairable bad chips, then laser repair
13
the repairable bad chips to good chips and finally test (
2
)
18
them to make sure they are good chips, finally dice the wafer
14
and obtain a plurality of good chips. At the rear section of the! packaging and testing factory, in order to enable the chips become suitable packaging structure, package the good chips
15
(such as the packaging type of SOP, DIP, QFP or BGA). After packaging usually execute the final testing (
1
)
16
for making sure if the packaged chips can imitate deteriorating burn-in operation, pick the bad chips out in advance and prevent damaging the equipment of burn-in, then perform the burn-in
17
. After burn-in execute final testing (
2
)
18
, examine and sort the chips which are well-packaged and through burn-in, thereafter execute pre-shipment inspection
19
such as marking, final testing (
3
), and check before shipping, after the processes mentioned above the modular assembling process can be continuously executed. In fact there are difficulties for too many manufacturing steps and having to perform multi-testing and multi-examination to maintain the quality in the manufacturing process. Besides, after being packaged in the packaging and testing factory the chips can not be laser repaired any more for the packaging thickness and uneasy to keep position in the package body so that the ratio of good chips is unable to be increased efficiently.
A testing process of semiconductor devices is described from U.S. Pat. No. 5,326,709 entitled “WAFER TESTING PROCESS OF A SEMICONDUCTOR DEVICE COMPRISING A REDUNDANCY CIRCUIT”. Wherein the semiconductor device has a redundancy circuit, at first partially etch PSG film and nitride film on a wafer for opening the bonding pads, thereafter execute “testing before laser repairing”, “laser repairing”, “testing repaired chips”, and “off-line inking” in order. The Patent mainly mentions about the link of testing and laser repairing process but nothing about burn-in process at all. The foregoing burn-in is to execute packaging, the defect is that the bad chips are unable to be repaired after packaging and bum-in mentioned above. Further, the Patent describes about wafer testing process for bare chip that is different from the present manufacturing process for flip-chip.
SUMMARY OF THE INVENTION
The main purpose of the present invention is to supply a manufacturing process of semiconductor devices, execute testing and repairing after bumping in order to shorten the testing process and increase the ratio for good chips.
In accordance with the present invention of manufacturing process of semiconductor devices mainly comprises:
(a) providing a wafer, the wafer includes a plurality of chips non-diced;
(b) forming a plurality of bumps in the wafer;
(c) testing the wafer for distinguishing repairable chips;
(d) laser repairing the repairable chips mentioned above; and
(e) dicing the wafer for obtaining a plurality of flip-chip-typed chips being through burn-in and testing.
Thereby achieve uniting the front and rear manufacturing process of semiconductor and the efficacy for increasing the ratio of good chips.


REFERENCES:
patent: 5326709 (1994-07-01), Moon et al.
patent: 5657280 (1997-08-01), Shin et al.
patent: 5904859 (1999-05-01), Degani
patent: 5910678 (1999-06-01), Lou et al.
patent: 5977632 (1999-11-01), Beddingfield
patent: 6101618 (2000-08-01), McClure
patent: 6121073 (2000-09-01), Huang et al.
patent: 6233184 (2001-05-01), Barth

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