Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-31
2004-03-23
Thompson, Craig A. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S912000, C257S104000
Reexamination Certificate
active
06709914
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Technical field of the Invention
The present invention relates to an pn junction diode device and a manufacturing process thereof, and in particular to the pn junction diode device having less deviation of forward voltages between the devices and the manufacturing process thereof.
2) Description of Related Arts
FIG. 9
is a cross sectional view of a conventional pn junction diode device denoted by a reference numeral
200
, which can be used as a switching device as well as a transistor. As illustrated in
FIG. 9
, the pn junction diode device
200
has a stacked structure including, in general, an n+ cathode layer
1
, an n− cathode layer
2
, and a p− anode layer
3
. A pn junction interface
4
is formed at the interface between the n− cathode layer
2
and the p− anode layer
3
. Each of the aforementioned layers is made of material including silicon.
Deposited on the top surface of the p− anode layer
3
is an anode electrode
5
, while formed on the bottom surface of the n+ cathode layer
1
is a cathode electrode
6
. Each of the electrodes is made of material such as aluminum.
The pn junction diode device
200
has a lattice-defect region
17
in the n− cathode layer
2
formed beneath and adjacent to the pn junction interface
4
. In the lattice-defect region, a plurality of defective lattices are distributed in accordance with a normal distribution having a half-value width T. The lattice-defect region
17
is formed by implanting ions such as proton and helium ion after formation of the layers
1
to
6
, and by annealing thereof. In general, this ion implanting step is conducted through a absorber
8
made of aluminum. During the annealing step, most of the implanted ions are evacuated from the n− cathode layer
2
, leaving the lattice-defect region
17
. The half-value width T may be distributed, for example, about 10 microns in the depth direction.
FIG. 10
is a graph illustrating carrier concentrations and a lattice-defect concentration depending upon the vertical distance (depth) from the top surface of the pn junction diode device
200
. Thus, the anode and cathode electrodes
5
,
6
are located to the left and right sides in
FIG. 10
, respectively. Also, the denotations of “p”, “n”, and “q” in
FIG. 10
indicate the distributions of the p-type and n-type impurity concentrations and the lattice-defect concentration, respectively. The Roman numerals I, II, and III denote regions for the p− anode layer
3
, the n− cathode layer
2
, and the n+cathode layer
1
, respectively.
In
FIG. 10
, the lattice-defect region
17
is formed adjacent to the pn junction interface and within the n− cathode layer (II), and has the half-value width T.
The lattice-defect region
17
serves a function as so-called a “life-time killer”, thus, it captures and quenches the minority carriers, i.e., holes injected from the p− anode layer
3
into the n− cathode layer
2
. To this end, the pn junction diode device
200
can be protected from a reverse surge potential and a high rate switching can be realized.
Each of the conventional pn junction diode devices
200
is manufactured by forming a plurality of devices formed on the semiconductor wafer having a diameter of 5 inches and then by dicing the wafer to each individual pn junction diode device. Disadvantageously, there exists a substantial deviation of forward voltages (V
F
) between the pn junction diode devices
200
formed even on the same wafer.
The present inventors have dedicated to study the deviation of the forward voltages and found that this is caused by the deviation of the lattice-defect concentration in the lattice-defect region
17
. Also, the present inventors have revealed that the deviation of the lattice-defect concentration can be reduced by expanding the half-value width and reducing the peak concentration, maintaining the total number of the defective lattices unchanged in the lattice-defect region
17
.
However, in order to expand the half-value width of the lattice-defect region
17
, in general, it is necessary to repeat the ion implantation steps with implantation energies different from each other for achieving individual projection ranges. Such a multiple of ion implantation steps cause the manufacturing process to be lengthy and complicated, thereby raising the manufacturing cost.
Therefore, one of the aspects of the present invention has an object to provide the manufacturing process of the pn junction diode device with the lattice-defect region having the wider half-value width without increasing any implantation steps, and to provide the pn junction diode device so manufactured.
SUMMARY OF THE INVENTION
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the sprit and scope of the invention will become apparent to those skilled in the art from this detailed description.
The first aspect of the present invention is to provide a process for manufacturing a pn junction diode, includes providing a semiconductor wafer having an n-type cathode layer formed thereon. Then, a p-type anode layer is formed on the n-type cathode layer so that a pn junction interface is formed between the n-type cathode layer and the p-type anode layer. Next, a cathode and anode electrodes are formed on the semiconductor wafer and the p-type anode layer, respectively. Lastly, first and second ions having average projection ranges Rp different from each other are simultaneously implanted up to the cathode layer so that one or more first and second implanted regions are formed alternately and overlapped side by side, thereby forming a lattice-defect region having a substantially uniform thickness.
The second aspect of the present invention is a to provide a pn junction diode includes a semiconductor wafer having an n-type cathode layer. Also, a p-type anode layer is formed on the n-type cathode layer so that a pn junction interface is formed between the n-type cathode layer and the p-type anode layer. A cathode and anode electrodes are formed on the semiconductor wafer and the p-type anode layer, respectively. Lastly, a lattice-defect region in the n-type cathode layer having a substantially uniform thickness is formed beneath and adjacent to the pn junction interface. The lattice-defect region has a distribution of lattice-defect concentration with a half-value width greater than that of the lattice-defect region formed by implanting ions having an average projection ranges Rp substantially the same as each other.
REFERENCES:
patent: 0 878 849 (1998-11-01), None
patent: 4-214674 (1992-08-01), None
patent: 10-116998 (1998-05-01), None
Derwent Abstract Publication No. JP 07235663A Matsushita Electric Works Ltd. Feb. 1994.
Ishizawa Shinichi
Tomomatsu Yoshifumi
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