Manufacturing process of an interpoly dielectric structure...

Details Manufacturing process of an interpoly dielectric structure... Manufacturing process of an interpoly dielectric structure...

2006-08-01

2006-08-01

Richards, N. Drew (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S264000

Reexamination Certificate

active

07084032

ABSTRACT:
A process manufactures an interpoly dielectric layer for non-volatile memory cells of a semiconductor device with an interpoly dielectric layer. The process begins with forming the tunnel oxide, and hence the amorphous or polycrystalline silicon layer, using conventional techniques. After the amorphous or polycrystalline silicon layer is surface cleansed and passivated, the surface of the polycrystalline layer is nitrided directly by using radical nitrogen. This is followed by the formation of the interpoly dielectric, either as an ONO layer or a single silicon layer, by means of the CVD technique. Masking to define the floating gate may be performed immediately before or after the direct nitridation step is carried out. The equivalent electrical thickness of the interpoly dielectric, obtained by combining the nitride oxide layer and by the following dielectric, does not exceed 130 Angstroms in either the ONO layer or the single silicon layer embodiment.

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