Manufacturing process of a MOS semiconductor device

Details Manufacturing process of a MOS semiconductor device Manufacturing process of a MOS semiconductor device

1996-11-08

1998-06-23

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438302, H01L 2170

Patent

active

057704910

ABSTRACT:
In a manufacturing process of a MOS FET having a C-MOS structure, lightly doped n- diffused layer is formed for source/drain regions in n channel and p channel transistor regions respectively. A p+ diffused layer is further formed for source/drain regions in a p channel transistor region. By a heating process, the n- layer is outweighed by diffusion of p type impurities in the p channel transistor region, and the source/drain current of the p channel MOS FET is secured.

REFERENCES:
patent: 4599789 (1986-07-01), Gasner
patent: 4764477 (1988-08-01), Chang et al.
patent: 4908327 (1990-03-01), Chapman
patent: 5217910 (1993-06-01), Shimizu et al.
patent: 5413945 (1995-05-01), Chien et al.
patent: 5516711 (1996-05-01), Wang
patent: 5532176 (1996-07-01), Katada et al.

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