Manufacturing process of a germanium implanted HBT bipolar...

Details Manufacturing process of a germanium implanted HBT bipolar... Manufacturing process of a germanium implanted HBT bipolar...

2000-11-27

2003-09-23

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S312000, C438S315000

Reexamination Certificate

active

06624017

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to a process for fabricating a vertical structure high carrier mobility transistor on a crystalline silicon substrate, having a collector region located at a lower portion of the substrate.
The invention relates, particularly but not exclusively, to a process for fabricating a heterostructure bipolar transistor (HBT) for very high frequency applications, and the description to follow is given with reference to this applicational field for convenience of illustration.
BACKGROUND OF THE INVENTION
As skilled persons in the art know well, the application of heterostructures to solid state electronic devices has prompted a vast increase of their working range at very high frequencies.
In particular, this technology has been applied to bipolar transistor devices, to thereby improve both the injection efficiency of the charge carriers and the passage frequency (f
t
) value, the latter being closely related to the cut-off frequency (f
T
) of the device.
Heterostructures can be prepared by different methods, of which the MBE (Molecular Beam Epitaxy) method is the best known and provides a structure free of lattice imperfections; other, more expensive methods are sophisticated versions of CVD which, however, have a disadvantage in that their throughput adds to the cost of the silicon die.
Yet this MBE method has only sparsely been applied to large volume industrial processes, on account of it involving lengthy processing steps that command strict control of their physical parameters.
Thus, it has often been more convenient to adopt other methods, such as ion implantation, which could yield similar heterostructures of a fair quality within acceptable times for large volume production lines.
A bipolar transistor implemented with a vertical structure including a Ge
x
Si
1−x
heterostructure between the base and collector regions will now be described in relation to such a field of application.
The HBT bipolar transistor under consideration is illustrated schematically by the enlarged cross-sectional view of FIG.
1
.
This HBT transistor has a vertical structure of the NPN type and is formed on a crystalline semiconductor substrate
1
wherein, by successive implantations, a collector region
2
of the N type, a base region
3
of the P type, and an emitter region
4
of the N type have been defined, from the substrate bottom up.
Specifically, it can be seen that the collector region
2
includes a heavily N-doped layer
5
effective to provide a good ohmic contact with a collector metal (not shown because conventional) provided in a lower portion of the substrate
1
.
An added feature of the HBT transistor shown in
FIG. 1
is an opening provided above the substrate
1
to isolate the base region
3
and later allow formation of a contact region
9
above the emitter region
4
.
This contact region
9
comprises a heavily N-doped layer
7
overlaid by a metal layer
8
.
Having briefly described the HBT transistor, the Ge
x
Si
1−x
heterostructure formed within the crystalline silicon substrate
1
will now be examined to see what changes are introduced in the energy band curve of the HBT transistor.
This Ge
x
Si
1−x
heterostructure is characterized by the x and
1
-x concentrations, respectively associated with the germanium and silicon atoms, varying with the spatial implant depth in the substrate
1
.
In
FIG. 2
, the energy band curve of the bipolar transistor HBT is plotted as a full line for comparison with the band curve of a standard bipolar transistor (BJT), plotted as a broken line.
A comparison of the two band curves of the transistors HBT and BJT shows that the bipolar transistor HBT has an energy level in the conduction band which is always below that of the standard transistor BJT, through the base region to the interface with the collector region.
In particular, it can be seen that for the transistor HBT, when moving from its base region toward its collector region, there occurs a gradual slow decrease of its energy gap (E
g
) which can be regarded as an effect of spatial modulation of the energy gap. This modulation is obtained by suitable implantation profiles of the germanium (Ge) atomic species whose concentration is maximal at the collector-base interface and minimal or almost nil at the emitter-base interface.
An active zone bias of the bipolar transistor HBT conforming with the above band curve allows of faster injection of the carriers from the emitter region, thereby greatly reducing their passage time.
The net result is a markedly increased cut-off frequency (f
T
) of the HBT transistor and a decreased proportion of carriers trapped within the base.
Thus, for HBT transistors biased with collector currents in the milliampere range, high cut-off frequency values can be obtained which would not be achievable by conventional bipolar technology.
The Ge
x
Si
1−x
heterostructure provided between the base and collector regions enables the P-doping of the base region to be increased, thereby lowering the value of the intrinsic resistance R
bb
in the base region that restricts the applications of bipolar transistors at high frequencies.
A previously mentioned method of conventionally forming the HBT transistor with a Ge
x
Si
1−x
heterostructure will now be described with reference, in particular, to
FIGS. 3
a
-
3
f
. The same reference numerals used for similar elements in
FIG. 1
have been retained for convenience.
FIG. 3
a
shows a crystalline silicon substrate
1
which has been doped with impurities of the N type and formed with a window
10
by selective deposition of a protective material
11
. This protective material comprises a material layer, including impurities of the P type, which is deposited over the substrate and insulated by a dielectric capping.
A first implantation of germanium (Ge) is carried out through this window
10
, and is followed by a second implantation of acceptor impurities, such as boron (B) atoms or BF
2
+
ions.
Thereafter, a step of re-construction of the crystal lattice of the substrate is carried out by an RTA (Rapid Thermal Annealing) process, or a conventional thermal process in an oven, which is also applied to aid in driving the implanted ions into sites freed in the crystal lattice.
The outcome of this re-construction step is shown in
FIG. 3
b
, where a planar base region
3
, extending at the window
10
to a sufficient depth to allow of the subsequent creation of an emitter region, is highlighted for the first time.
Simultaneously with the formation of the base region
3
in the substrate
1
, a collector region
2
is defined which is incorporated to the remaining portion, not implanted with P-type impurities, of the substrate
1
.
The base region, extending as far as the interface to the collector region
2
, will presently feature a Ge
x
Si
1−x
heterostructure formed during the first implanting step and characterized by an energy band curve of the kind shown in FIG.
2
.
From now on, as shown in
FIG. 3
c
, the processing over the substrate
1
, at the location of the window
10
and the protective material
11
, will see the following successive operations:
thermal growth of a first thin dielectric layer
12
of silicon dioxide (SiO
2
);
deposition of a second dielectric layer
14
, typically of silicon nitride (Si
3
N
4
), onto the first thin dielectric layer
12
;
deposition of a polysilicon layer
15
.
To provide an emitter region at the location of the window
10
in the substrate
1
, the process for fabricating the HBT transistor comprises a first chemio-physical etching (RIE) step and a second etching step, respectively of the polysilicon layer
15
and the second dielectric layer
14
, to partially form isolation spacers at the edges of the window
10
, as shown in
FIG. 3
d.
A third wet etching step of the remaining portions of the polysilicon layer
15
, and a fourth etching step of the first thin dielectric layer
12
only, bring to completion the formation of the spacers
50
, thereby exposing the base region
3
again,

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