MANUFACTURING PROCESS FOR THE INTEGRATION IN A SEMICONDUCTOR...

Details MANUFACTURING PROCESS FOR THE INTEGRATION IN A SEMICONDUCTOR... MANUFACTURING PROCESS FOR THE INTEGRATION IN A SEMICONDUCTOR...

2001-05-15

2002-09-17

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S241000, C438S266000, C257S326000

Reexamination Certificate

active

06451653

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the field of integrated circuit technology, and more specifically to the manufacturing of high-density integrated circuits, typically semiconductor memories, particularly but not exclusively non-volatile ones, and logic circuits. Still more specifically, the invention relates to a manufacturing process for the integration in same chip of a high-density integrated circuit portion, typically a memory, and high-performance logic integrated circuit portion.
BACKGROUND OF THE INVENTION
As known, in a semiconductor memory the most of the chip area is occupied by the array of memory cells, the so-called memory matrix. Thus, in order to keep the chip dimensions small enough while the number of memory cells increases, the dimensions of the memory cells have to be shrunk, so as to pack more and more memory cells per chip unit area.
However, one of the factors that limits the possibility of shrinking the memory cells' dimensions is the possibility of reducing the dimensions of the contacts. In a memory matrix, a large number of contacts are provided, e.g,. for contacting the memory cells' drain regions by the metal bit lines. Current memory chips can have several tens of millions of contacts.
The reason why the contact dimensions cannot be easily shrunk is mainly lithographic, and gives rise to an increased defectivity, that is, a low production yield.
In recent years, several new techniques of forming contacts have been proposed, in the attempt to shrink the contact dimensions without increasing the defectivity of the memory chips. One of such new techniques is the so-called Self-Aligned Contact (shortly, SAC) technique, in which by using an anisotropic etch non-conductive layers are advantageously used to relax the contact mask design rules.
However, new difficulties now arise in view of the trend towards the integration in a same semiconductor chip of a semiconductor memory and high-performance logic circuits, for the reasons to be explained.
Conventionally, high-performance logic circuits take advantage of another technique, known as salicidation, or self-aligned silicidation, providing for a self-aligned formation of metal suicides on active areas and on polysilicon layers. The use of salicidation has made possible higher circuit performance.
Thus, the general practice now provides for using the SAC technique for the fabrication of semiconductor memories, and salicidation for the production of high-performance logic circuits.
Unfortunately, the above two techniques are scarcely compatible. This prevents or makes difficult the integration in a same chip of a memory and high-performance logic circuits.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides a manufacturing process suitable for integrating in a same semiconductor chip a high-density integrated circuit portion and a high-performance logic integrated circuit portion.
The process includes:
over a semiconductor substrate, insulatively placing a silicidated polysilicon layer, comprising a polysilicon layer selectively doped in accordance to a conductivity type of at least the high-performance logic integrated circuit components, covered by a silicide layer;
selectively covering the silicidated polysilicon layer with a hard mask;
defining gate structures for the high-density integrated circuit components and for the high-performance logic integrated circuit components using said hard mask, the gate structures comprising the silicidated polysilicon layer covered with the hard mask; and
in a dielectric layer formed over the chip, forming contact openings for electrically contacting the high-density integrated circuit components and the high-performance logic integrated circuit components, wherein at least the contact openings for electrically contacting the high-density integrated circuit components are formed in self-alignment with the gate structures thereof.


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