Manufacturing process for a DRAM with a buried region

Details Manufacturing process for a DRAM with a buried region Manufacturing process for a DRAM with a buried region

1997-06-09

1998-11-03

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438253, H01L 218242

Patent

active

058307915

ABSTRACT:
A semiconductor memory cell has a semiconductor substrate, an active region disposed on the semiconductor substrate and having two impurity regions, a gate electrode disposed on the active region, a field region isolated from the active region on the semiconductor substrate and having a contract hole, a capacitor disposed over the active region and field region on the semiconductor substrate, and a buried region disposed under the field region and the bit line contacting the first impurity region through the contact hole.

REFERENCES:
patent: 4961095 (1990-10-01), Mashiko
patent: 4987090 (1991-01-01), Hsu et al.
patent: 5012309 (1991-04-01), Nakayama
patent: 5014103 (1991-05-01), Ema
patent: 5108945 (1992-04-01), Matthews
patent: 5172202 (1992-12-01), Kazuo

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