Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-22
2002-02-05
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S198000, C438S199000, C438S592000
Reexamination Certificate
active
06344380
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a gate electrode structure using a conductive silicon layer and a manufacturing method thereof.
2. Description of the Related Art
As semiconductor devices require higher integration and higher performance, the size constraints of conductive layer patterns such as gate electrodes become more strict, i.e., they require conductors of smaller size. For instance, gate electrodes having sizes of 0.25 &mgr;m or 0.18 &mgr;m or less are required. Also, where the gate electrode is formed under very small size constraints, maintenance of the gate electrode uniformity and low critical dimension variations on a chip are required.
FIG. 1
is a schematic diagram illustrating a conventional gate electrode structure. Referring to
FIG. 1
, a gate electrode
30
is formed over a gate oxide layer
200
which is formed on a semiconductor substrate
100
. The gate electrode
30
is formed by patterning a polycrystalline silicon layer having conductivity obtained by doped impurities. The polycrystalline silicon layer is deposited at approximately 625° C. The polycrystalline silicon layer mostly consists of crystal grains.
Due to the crystal grains, a surface morphology of the polycrystalline silicon layer has fine flections as shown in FIG.
1
. For instance, an interface region between two crystal grains has a surface height lower than the surface of the crystal grain. This is caused by a difference between the interface energy and the surface energy or a difference in the tension stresses. Thus, surface roughness of the polycrystalline silicon layer is increased.
Accordingly, when a photoresist layer is formed on the polycrystalline silicon layer for a gate electrode, and then exposure is performed, the incident light exposing the photoresist layer may be diffusely reflected. As a result, a photoresist pattern having irregular critical dimensions can be formed on the polycrystalline silicon layer.
When the polycrystalline silicon layer is patterned using the photoresist pattern with the irregular critical dimensions as an etch mask, a polycrystalline silicon layer pattern having the irregular critical dimension may be formed. That is, a polycrystalline silicon layer pattern
30
having a dimension
35
wider or narrower than the designed critical dimension
31
is formed. Also, a sidewall profile of the formed polycrystalline silicon layer pattern
30
is not uniform.
When the critical dimension of the polycrystalline silicon layer pattern
30
used for the gate electrode is changed, a process margin of the subsequent step is reduced, or the operation of a transistor may be degraded. More specifically, as the critical dimension of the gate electrode is changed, gate resistance is changed, and thus the operation current of the transistor is changed, which may cause failure in the operation of the transistor or reduction in the operational speed.
SUMMARY OF THE INVENTION
It is a first objective of the present invention to provide a gate electrode structure of a semiconductor device having a uniform critical dimension by improving a surface morphology.
It is another objective of the present invention to provide a method for manufacturing a gate electrode structure of a semiconductor device in which a surface morphology is improved to suppress a change of a critical dimension of the gate electrode.
Accordingly, to achieve the first objective, according to an aspect of the present invention, a gate electrode structure of a semiconductor device is provided. The structure includes a gate oxide layer formed on a semiconductor substrate and a first silicon layer pattern of polycrystalline silicon formed on the gate oxide layer. A second silicon layer pattern having surface roughness lower than that of the first silicon layer pattern is formed on the first silicon layer pattern. In one embodiment, the second silicon layer pattern includes crystal grains smaller than those of the first silicon layer pattern. Specifically, in one embodiment, the first silicon layer pattern has the crystal grains having sizes of approximately 100~300 Å. In one embodiment, the second silicon layer pattern is an amorphous silicon layer having crystal grains smaller than those of the first silicon layer pattern. The amorphous silicon layer pattern can have crystal grains with a size of approximately 40 Å or less.
The first silicon layer pattern can be a polycrystalline silicon layer pattern formed at approximately 580~650° C., and the second silicon layer pattern can be an amorphous silicon layer pattern formed at approximately 560~580° C. In another embodiment, the first silicon layer pattern is a polycrystalline silicon layer pattern formed at approximately 600~650° C., and the second silicon layer pattern is a silicon layer pattern formed at approximately 580~600° C.
To achieve the second objective, according to an aspect of the present invention, a gate oxide layer is formed on a semiconductor substrate. The step of forming the first silicon layer comprises the step of depositing silicon at approximately 580~650° C. to thereby form the first silicon layer.
A second silicon layer having the low surface roughness is formed on the first silicon layer. The step of forming the second silicon layer comprises the step of forming an amorphous silicon layer on the first silicon layer, and the step of forming the amorphous silicon layer comprises the step of depositing silicon at approximately 560~580° C. Preferably, silicon is deposited at approximately 560~570° C.
The step of forming the first silicon layer and the step of forming the second silicon layer can be performed by in-situ lowering the deposition temperature.
In one embodiment, the step of forming the first silicon layer comprises the step of depositing silicon at approximately 600~650° C. to thereby form a silicon layer of polycrystalline forming the second silicon layer can include depositing silicon at approximately 580~600° C. or less to thereby form a silicon layer having the surface roughness lower than that of the first silicon layer.
The second silicon layer and the first silicon layer are patterned to form a gate electrode.
According to the present invention, the gate electrode structure having a uniform critical dimension can be realized due to the good surface morphology of a conductive layer for the gate electrode. Thus, characteristics of a transistor can be stabilized.
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patent: 5457058 (1995-10-01), Yonehara
patent: 5767004 (1998-06-01), Balasubramanian et al.
patent: 5936262 (1999-08-01), Batra et al.
patent: 6017782 (2000-01-01), Batra et al.
patent: 2224223 (1990-09-01), None
patent: 3055850 (1991-03-01), None
Kim Hyeon-cheol
Shin Heon-jong
Mills & Onello LLP
Rao Shrinivas H.
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